Semiconductor News & Analysis Feed
13 articles
2026-07-22
xenospectrum.com
2026-07-22
Zeiss has highlighted China's significant gap in advanced EUV lithography technology, which becomes increasingly pronounced beyond the 7nm process node. As semiconductor manufacturing advances to smaller process nodes, production complexity intensifies across multiple dimensions including technical
2026-07-21
tomshardware.com
2026-07-21
Recent teardown analysis by SemiAnalysis of Huawei's Kirin 9030 chip revealed that SMIC's third-generation 7nm process (N+3) achieves a smaller metal pitch than Intel's 18A and surpasses TSMC's N6 in transistor density, despite not using EUV lithography. However, this does not make SMIC's N+3 proces
2026-07-21
www.tomshardware.com
2026-07-21
2026-07-12
www.indexbox.io
2026-07-12
2026-07-09
2026-06-27
simplywall.st
2026-06-27
Taiwan Semiconductor Manufacturing Company (TSMC) is raising prices for 7nm and below chip manufacturing processes by 5% to 10%, coinciding with its major expansion plans for wafer fabs and advanced packaging facilities through 2026. As a central player in global chip supply for AI and high-performa
2026-06-26
tomshardware.com
2026-06-26
IBM has achieved a major breakthrough in semiconductor manufacturing by developing the industry's first sub-1nm fabrication process, the 0.7nm-class technology. This innovation is based on a novel nanostack transistor architecture that delivers significant improvements in performance, power efficien
2026-06-26
www.tomshardware.com
2026-06-26
IBM has announced the development of the industry's first sub-1nm fabrication process, a 0.7nm-class technology based on nanostack transistors. Compared to its 2nm node, this new process delivers up to 50% higher performance and 70% better energy efficiency. The innovation uses a dual-wafer approach
2026-06-26
www.silicon.co.uk
2026-06-26
IBM has unveiled a new 3D-stacked 0.7nm chip design, dubbed the 'nanostack' architecture, which could enable processor geometries below 1 nanometer. This advancement allows for nearly 100 billion transistors to be packed into a fingernail-sized area, doubling the density of IBM's previous 2nm chip.
2026-06-26
www.silicon.co.uk
2026-06-26
IBM has unveiled its new 0.7nm chip design, dubbed the 'nanostack' architecture, which promises to fit nearly 100 billion transistors onto a fingernail-sized chip area. This advancement, developed amid rising demand for processing power in AI applications, outperforms IBM's previous 2nm chip by 50%
2026-06-26
letsdatascience.com
2026-06-26
IBM unveiled the world's first sub-1 nanometer chip technology on June 25, 2026, introducing the 0.7nm (7 angstrom) Nanostack 3D transistor architecture. This breakthrough enables nearly 100 billion transistors on a fingernail-sized die—nearly double the density of IBM's 2nm chip from 2021. The desi
2026-06-25
morethanmoore.substack.com
2026-06-25
IBM announced its latest 0.7nm process node technology and introduced NanoStack, marking a significant step forward in the semiconductor industry's evolution beyond traditional Moore’s Law. Based on Gate-All-Around (GAA) architecture, the technology advances toward Complimentary FET (CFET) structure
2026-06-16
tomshardware.com
2026-06-16
SMIC's third-generation 7nm process achieves a metal pitch of 32.5nm, surpassing Intel's 18A node at 36nm, but overall transistor density lags by 38%. This finding comes from SemiAnalysis's first teardown from its new in-house lab, analyzing the HiSilicon Kirin 9030 chip found in Huawei's Mate 80. D