Semiconductor News & Analysis Feed

11 articles
2026-06-27
simplywall.st 2026-06-27 simplywall.st
United States/Semiconductors/NYSE:TSM TSMC (NYSE:TSM) Is Raising 7nm Chip Prices Up To 10% As Expansion Builds June 27, 2026 Simply Wall St Reviewed by Bailey Pemberton Share Copy Link TSMC is reported to be raising prices by 5% to 10% on 7nm and below chip manufacturing processes. The price changes target leading edge capacity used in AI, datacenter, and high performance computing chips. The comp
2026-06-26
tomshardware.com 2026-06-26 Anton Shilov
IBM's new 0.7nm-class fabrication process uses nanostack transistors, requires 2x more FEOL steps for massive improvements in performance, power, and area.
2026-06-26
www.tomshardware.com 2026-06-26 Tom's Hardware
Tech Industry Manufacturing Semiconductors IBM goes sub-1nm, develops 0.7nm-class technology — offering up to 50% higher performance and 70% higher energy efficiency compared to IBM's 2nm-class node News By Anton Shilov published June 26, 2026 It uses two wafers instead of one, along with ultra-thin dielectric bonding (Image credit: IBM) Share this article 5 Join the conversation Follow us Add
2026-06-26
www.silicon.co.uk 2026-06-26 Silicon UK
IBM Unveils 3D-Stacked .7nm Chip Design IBM says ‘nanostack’ approach could fit nearly 100 billion transistors into fingernail-sized area, amid soaring demand for processing power BY MATTHEW BROERSMA, JUNE 26, 2026, 8:30 AM 2 MIN IBM said a new chip design it has developed could enable processor geometries of under 1 nanometre, potentially enabling significantly more powerful and efficient chi
2026-06-26
www.silicon.co.uk 2026-06-26 Silicon UK
IBM Unveils 3D-Stacked .7nm Chip Design IBM says ‘nanostack’ approach could fit nearly 100 billion transistors into fingernail-sized area, amid soaring demand for processing power BY MATTHEW BROERSMA, JUNE 26, 2026, 8:30 AM 2 MIN IBM said a new chip design it has developed could enable processor geometries of under 1 nanometre, potentially enabling significantly more powerful and efficient chi
2026-06-26
digitimes.com 2026-06-26
On June 25, IBM unveiled what it calls the world's first sub-1nm chip technology: a 0.7nm — or 7 angstrom — transistor architecture built on an entirely new 3D platform called Nanostack. The announcement, timed to the VLSI 2026 symposium, marks the first time logic technology has extended below the 1nm node and, IBM says, opens a roadmap of at least a decade of further semiconductor scaling.
2026-06-26
letsdatascience.com 2026-06-26 Let's Data Science
INFRASTRUCTURE semiconductors ibm sub 1nm IBM debuts 0.7nm Nanostack with nearly 100B transistors 5 sources | June 25, 2026 8.5 Relevance Score Photo: storagereview.com · rights & takedowns QUICK SUMMARY Hide IBM unveiled the world's first sub-1 nanometer chip technology on June 25, 2026, using a new 0.7nm "Nanostack" 3D transistor architecture (also called 7 angstrom). The chip packs nearly 100
2026-06-25
morethanmoore.substack.com 2026-06-25 More Than Moore
Discover more from More Than Moore The latest in semiconductors: silicon, AI, processors, market trends. Over 12,000 subscribers Subscribe By subscribing, you agree Substack's Terms of Use, and acknowledge its Information Collection Notice and Privacy Policy. Already have an account? Sign in IBM Announces 0.7nm Process Node, Introduces NanoStack 666 Million Transistors Per Square Millimeter DR. IA
2026-06-24
tomshardware.com 2026-06-24 Etiido Uko
TSMC has reportedly told customers to prepare for 5% to 10% price hikes across advanced chip nodes, extending beyond 3nm to include 7nm and some legacy processes.
2026-06-18
digitimes.com 2026-06-18
A teardown of Huawei's latest Mate 80 Pro Max smartphone has put China's semiconductor progress back under scrutiny, after analysis showed the HiSilicon Kirin 9030 processor was made on SMIC's third-generation 7nm-class N+3 process with a local metal pitch narrower than that of Intel's 18A chip used in Panther Lake.
2026-06-16
tomshardware.com 2026-06-16 Luke James
SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm.