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2026-07-08
SUSE, Openchip partner to develop European RISC-V hardware - Evertiq
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evertiq.com 2026-07-08 Evertiq
2026-07-07
World working together ‘as one ecosystem’ on RISC-V chip research: executive - South China Morning Post
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www.scmp.com 2026-07-07 South China Morning Post
2026-07-07
World working together ‘as one ecosystem’ on RISC-V chip research: executive - South China Morning Post
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www.scmp.com 2026-07-07 South China Morning Post
2026-07-07
Modder builds 8,192-core GPU at home out of RISC-V microcontrollers
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tomshardware.com 2026-07-07 Bruno Ferreira
Well-known engineer Matthias Balwierz (aka Bitluni) designed and created an 8,192-core RISC-V GPU at home.
RISC-VmicrocontrollerGPUopen-source hardwareDIY projecthardware hackerembedded systems3D printing
2026-07-07
Modder builds 8,192-core GPU at home out of RISC-V microcontrollers — full "graphics card" draws over 2,000 watts of power, requires a 3D printer to program - Tom's Hardware
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www.tomshardware.com 2026-07-07 Tom's Hardware
2026-07-07
Madlad builds homebrew GPU using 8,192 RISC-V chips - The Register
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www.theregister.com 2026-07-07 The Register
2026-07-07
MIPS Software to Silicon with RISC-V. Interview with MIPS: “Physical AI is Agentic AI at the Edge”
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eetimes.com 2026-07-07
MIPS bets RISC-V and ARC AI will power physical AI in cars and factory robots. Watch the interview and learn more.
MIPSRISC-VPhysical AIAI ChipSemiconductor IPAutonomous MachinesRoboticsChip Design
2026-07-07
MIPS Software to Silicon with RISC-V. Interview with MIPS: “Physical AI is Agentic AI at the Edge” - EE Times
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news.google.com 2026-07-07 EE Times
2026-07-04
Linux 7.2-rc2 Raising The Default RISC-V 64-bit CPU Limit To 256 Cores - Phoronix
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www.phoronix.com 2026-07-04 Phoronix
2026-07-03
Collaboration to integrate RISC-V and MicroLED silicon photonics into 3D stacking and Interposer for next-gen AI - Engineer Live
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news.google.com 2026-07-03 Engineer Live
2026-07-03
RISC-V Accelerates Physical AI Chips - Open Source For You
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www.opensourceforu.com 2026-07-03 Open Source For You
2026-07-02
RISC-V RVV Vector Performance Benchmarks With The SpacemiT K3 SoC - Phoronix
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www.phoronix.com 2026-07-02 Phoronix
2026-06-30
SUSE, Openchip Partner To Build Europe’s First Digitally Sovereign RISC-V Stack - Open Source For You
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www.opensourceforu.com 2026-06-30 Open Source For You
Blogs SUSE, Openchip Partner To Build Europe’s First Digitally Sovereign RISC-V Stack By Jiya Jay Singh - June 30, 2026 0 10 SUSE Logo (PRNewsFoto/SUSE) SUSE and Openchip have signed an MoU to native-certify enterprise software on European-designed RISC-V accelerators, offering an open alternative to overseas chip monopolies. SUSE, an open-source enterprise software group, and Openchip, a Spanis
RISC-VOpen SourceEuropean ChipsDigital SovereigntyChip IndependenceCloud ComputingArtificial IntelligenceData Security
2026-06-30
Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna) - Semiconductor Engineering
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semiengineering.com 2026-06-30 Semiconductor Engineering
Researchers from ETH Zurich, lowRISC, and University of Bologna published a technical paper titled “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.” This paper describes Croc, an open-source, customizable RISC-V SoC platform and teaching flow that lets students take domain-specific chip-design projects from architecture and RTL through physical
RISC-VOpen SourceChip DesignSemiconductor EducationSoC PlatformRTL DesignPhysical DesignSilicon Manufacturing
2026-06-30
Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI
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eetimes.com 2026-06-30
RISC-V heavyweights tackle physical AI, edge autonomy and TOPS-per-watt—watch how robots chase their killer app.
Physical AIRISC-VEcosystemEdge IntelligenceChip DesignAI HardwareEmbedded SystemsComputing Architecture
2026-06-30
Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI - EE Times
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news.google.com 2026-06-30 EE Times
2026-06-29
AheadComputing Positions RISC-V CPU Strategy Around AI Infrastructure Bottlenecks - TipRanks
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www.tipranks.com 2026-06-29 TipRanks
www.tipranks.com Performing security verification This website uses a security service to protect against malicious bots. This page is displayed while the website verifies you are not a bot. Ray ID: a17736143c7bdc5f Performance and Security by Cloudflare Privacy
RISC-VAI InfrastructureCPU ArchitectureSemiconductor ChipsArtificial Intelligence ComputingChip DesignTechnology StrategyComputing Architecture
2026-06-29
SUSE & Openchip back European RISC-V software stack - ChannelLife UK
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channellife.co.uk 2026-06-29 ChannelLife UK
VIRTUALISATION DATA PROTECTION DC SUSE & Openchip back European RISC-V software stack Mon, 29th Jun 2026 SEAN MITCHELL Publisher SUSE and Openchip have signed a memorandum of understanding to develop a European RISC-V hardware and open source software stack, centred on software support for processors designed in Europe. The work will focus on tuning SUSE Linux and Kubernetes products for Openchi
RISC-VOpen Source SoftwareEuropean SemiconductorData SovereigntyCloud ComputingContainerizationArtificial IntelligenceChip Design
2026-06-28
WCH CH32V006EVT board supports Zephyr for low-cost RISC-V development - LinuxGizmos.com
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linuxgizmos.com 2026-06-28 LinuxGizmos.com
Olimex recently featured the WCH CH32V006EVT, a low-cost evaluation board for the RISC-V-based CH32V006K8U6 microcontroller. The board is designed around WCH’s CH32V006 family and provides a compact platform for experimenting with the QingKe V2C 32-bit RISC-V core, Zephyr support, and basic embedded development features. The CH32V006K8U6 integrates a QingKe V2C processor using the RV32EmC instruc
RISC-VMicrocontrollerZephyr OSEmbedded DevelopmentWCHCH32V006Open Source HardwareLow Power Design
2026-06-26
One man, two kernels, and a lot of RISC-V - The Register
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www.theregister.com 2026-06-26 The Register
SOFTWARE One man, two kernels, and a lot of RISC-V A homebrew PC and mini-mainframe were only the warm-up for Yuri Zaporozhets' latest operating system Liam Proven 15 Published Fri 26 Jun 2026 // 13:46 UTC Yuri Zaporozhets of QRV Systems is a busy chap. He's built a new RISC-V-based personal computer, a mainframe on an FPGA, and rewritten QNX – twice. Seemingly every month or two, The Reg FOS
RISC-VOpen Source Operating SystemQNXFPGAEmbedded SystemsFree SoftwareMicrokernelSystem Design