Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna) - Semiconductor Engineering

Researchers from ETH Zurich, lowRISC, and the University of Bologna have introduced Croc, an open-source, customizable RISC-V SoC platform designed to train the next generation of chip designers throu... Read original →

The Croc platform catalyzes RISC-V’s evolution from academic toy to industrial-grade IP reuse. Technically, its end-to-end open flow pressures EDA vendors like Synopsys to expose more APIs as open-source tools (Yosys, OpenROAD) mature rapidly. From a compliance angle, it sidesteps U.S. export controls on advanced-node EDA, offering Taiwan, China; mainland China; and European institutions a geopolitically neutral training stack. Strategically, Arm may slash education licensing fees or launch a stripped-down Mbed OS to retain talent, while Cadence could acquire open-source EDA startups preemptively. Within 12–24 months, expect regional 'chip micro-factories'—university-fab partnerships enabling rapid tape-outs—eroding traditional IDMs’ monopoly on entry-level engineer development.