IBM goes sub-1nm, develops 0.7nm-class technology

IBM has achieved a major breakthrough in semiconductor manufacturing by developing the industry's first sub-1nm fabrication process, the 0.7nm-class technology. This innovation is based on a novel nan... Read original →

IBM’s 0.7nm breakthrough represents a strategic pivot—bypassing High-NA EUV by redefining transistor architecture via nanostack vertical CMOS integration. This shift forces EDA and materials suppliers to overhaul 3D design rule sets, while AI chipmakers may fast-track co-development to capture its 70% power efficiency gain. Although it sidesteps ASML’s next-gen lithography bottleneck, the approach introduces severe yield challenges in wafer bonding and alignment, likely doubling manufacturing costs—limiting near-term adoption to high-margin HPC. TSMC and Samsung face pressure to accelerate CFET roadmaps, yet their massive GAA investments constrain agility. Within 18 months, the U.S. could weaponize this advance by expanding export controls to cover nanostack-related tools and IP, deepening fragmentation in global semiconductor innovation.