Semiconductor News & Analysis Feed

IBM's unveiling of sub-1nm chip technology at the 2026 VLSI symposium represents a significant breakthrough in semiconductor manufacturing, introducing the world's first 0.7nm transistor architecture built on the novel 3D Nanostack platform. This advancement addresses fundamental physical limitation

IBM has unveiled its novel Nanostack transistor technology aimed at sub-1nm chips, marking a significant leap in semiconductor design beyond traditional 2D layouts. This 3D-like architecture vertically stacks and staggers transistors, enabling a density nearly twice that of IBM's 2nm chip, with near

IBM unveiled the world's first sub-1 nanometer chip technology on June 25, 2026, introducing the 0.7nm (7 angstrom) Nanostack 3D transistor architecture. This breakthrough enables nearly 100 billion transistors on a fingernail-sized die—nearly double the density of IBM's 2nm chip from 2021. The desi

IBM has made a significant breakthrough in sub-1-nanometer chip technology with its new NanoStack transistor architecture, promising enhanced computing performance, memory density, and energy efficiency. Unlike traditional process nodes, NanoStack focuses on a 3D integration approach that vertically

IBM announced its latest 0.7nm process node technology and introduced NanoStack, marking a significant step forward in the semiconductor industry's evolution beyond traditional Moore’s Law. Based on Gate-All-Around (GAA) architecture, the technology advances toward Complimentary FET (CFET) structure

IBM Research has introduced a breakthrough chip architecture called the nanostack, designed to overcome the spatial limitations of traditional two-dimensional scaling in semiconductor devices. By stacking silicon wafers and transistors vertically, this 3D approach dramatically increases transistor d