What is a nanostack? Building a chip like a city - IBM Research

IBM Research has introduced a breakthrough chip architecture called the nanostack, designed to overcome the spatial limitations of traditional two-dimensional scaling in semiconductor devices. By stac... Read original →

IBM’s nanostack redefines Moore’s Law by shifting from lateral scaling to vertical integration, leveraging wafer-level bonding and High NA EUV to stack transistors—effectively doubling density beyond 2nm nodes. This forces ASML to accelerate High NA EUV deployment and compels EDA vendors to overhaul 3D parasitic extraction tools. Geopolitically, tighter U.S. export controls on advanced packaging gear could hinder Chinese foundries like SMIC from accessing heterogeneous integration capabilities. Intel may fast-track integration of backside power delivery with its RibbonFET, while TSMC (Taiwan, China) likely doubles down on SoIC to preserve 2D scaling leadership. Within 18 months, thermal density, TSV yield, and interlayer stress will dominate R&D agendas, with AI accelerators leading adoption of vertically partitioned logic blocks.