IBM Unveils 3D-Stacked .7nm Chip Design - Silicon UK

IBM has unveiled a new 3D-stacked 0.7nm chip design, dubbed the 'nanostack' architecture, which could enable processor geometries below 1 nanometer. This advancement allows for nearly 100 billion tran... Read original →

IBM’s 0.7nm 'nanostack' isn’t just a scaling milestone—it forces EDA, advanced packaging, and EUV ecosystems to confront unprecedented TSV and hybrid bonding yield demands. Geopolitically, if production materializes within five years, U.S. export controls could expand to cover 3D integration IP, accelerating Japan-U.S. ventures like Rapidus to decouple from Taiwan, China-based manufacturing. Samsung may leverage IBM’s licensing to challenge TSMC’s dominance in HBM4+ stacks, while NVIDIA and Cerebras—already deploying dense SRAM on TSMC’s 4/5nm—face architectural obsolescence risk. Within 18 months, AI chip buyers will be forced to choose between raw density and geopolitically viable fabrication, turning Moore’s Law into a proxy for tech sovereignty.