English translations of the《半导体深水区》column — semiconductor supply chain, advanced packaging, memory and interconnect. 30 article(s). RSS
ACM Research disclosed a voluntary announcement on the evening of September 30: as of September 29, 2026, total backlog reached 17.073 billion yuan, up 88.20% year-over-year, equivalent to approximately $2.5 billion. Par
Renesas released the TP65H020G4PLSGBD 650V GaN device, featuring 20mΩ on-resistance and an 8mm×8mm dual-side cooling PQFN package. The company claims it is the industry's first 650V dual-side cooling GaN for megawatt-sca
Four glass manufacturers have standardized on either 510x515mm or 515x510mm, driven by existing equipment and display glass supply chains, despite unresolved process route convergence.
Biren's next-generation chip is currently in the critical pre-production phase, akin to a restaurant's soft opening, where final validation and customer onboarding occur before full-scale delivery.
Two papers published in the same month give opposite verdicts on high-bandwidth flash (HBF). Whether it solves the KV cache bottleneck or creates a trap depends entirely on the scheduler.
Processor benchmarks can be optimized later, but interface certification schedules cannot be bypassed. Intel's next-generation platform has already completed this unavoidable step in advance.
Qorvo's new C-band radar front-end integrates BAW switch-filtering and high-efficiency GaN power amplifiers, eliminating discrete assembly for pulse ESA systems.
DeepSeek has rewritten its core training operators for Huawei's Ascend architecture and released them for free, directly targeting the most fortified segment of NVIDIA's CUDA ecosystem.
OpenAI selected AMD EPYC Turin as the host CPU for its in-house Jalapeño ASIC, prioritizing deployment maturity and operational stability over the latest platform.
Besi joins Applied Materials' $5 billion Silicon Valley center to bridge the gap between sub-micron bonding precision and legacy back-end assembly classifications.
Samsung has set HBM4 supply prices at over three times the current HBM3E rate, a move that will be locked in through annual contract negotiations with major AI customers.
Everspin demonstrated a CXL-connected MRAM system at SNIA SDC 2026, targeting checkpointing and persistent KV caches to reduce GPU idle time.
The internal structure of an AI accelerator chip simplifies to three components: a central compute die, adjacent HBM stacks, and a silicon interposer connecting them. The first two determine speed, while the third dictat
Silicon carbide devices stop at 6.5kV not due to process limits, but because higher voltages are uneconomical for this device type.
Tesla reduced memory on its AI5 and AI6 chips to secure sufficient supply for Optimus production, marking a first where memory constraints dictate chip design.
Three Japanese firms have agreed on the financial structure for a power semiconductor consolidation, but negotiations remain deadlocked over whether the new entity should focus exclusively on power devices or retain anal
Replacing copper wiring between dies with fiber optics is fundamentally a solution to the problem of distance.
NVIDIA is replacing superior PTFE with slightly inferior hydrocarbon resin CCL in its switch trays. The trade-off exchanges electrical performance margin for improved production line yield.
The Huawei Mate 90 launched on October 1, shifting focus from pricing to a 1.5-micron bonding pitch revealed in third-party packaging cross-sections.
A joint development pact between an equipment maker and a memory vendor usually signals either mature processes requiring customization or unresolved process windows. Kioxia's entry into Applied Materials' EPIC center fa
JSR's new facility in Chungcheongbuk-do handles only the final production step of EUV metal oxide photoresist, positioning itself near key customers to optimize supply chain logistics.
In a 40-product launch, the standout item is a 1200V silicon carbide MOSFET, not a compute chip. India's first semiconductor path is power devices.
Meta's Muse has turned server CPUs into a scarce commodity. While this may seem like a rebranding of inference demand, lead times and allocation data are validating the shift sooner than expected.
The same batch of large interposers fits nine on a circular wafer but sixteen on a square panel. The difference is not just seven units, but whether the production line is economically viable.
Long-term contracts, traditionally a buyer's insurance policy, have become a binding rope for both sides in the HBM market.
The next mobile chip race is about moving memory off the processor stack, not just shrinking process nodes.
Unimicron spent NT$10.088 billion to acquire an existing facility. The real signal is that the capacity expansion bottleneck has shifted from construction to material availability.
LB Semicon's capacity expansion prioritizes a temporary bonding and de-bonding (TBDB) line, a critical step for thinning power wafers to reduce resistance without breaking them.
JDI sells its Mobara fab to Shinko Electric Industries, a move analysts view as a strategic pivot from obsolete display capacity to high-value advanced packaging.
DB HiTek raised foundry prices twice this year, with Chinese customers facing 20-30% increases and Korean customers seeing about 10%. Pricing at the same 8-inch fab and BCD process varies based on client profitability.