Besi joins Applied Materials' $5 billion Silicon Valley center to bridge the gap between sub-micron bonding precision and legacy back-end assembly classifications.
On one side is 0.1-micron-level bonding alignment precision; on the other is the decades-old classification label of "back-end packaging." The actual technical level of advanced packaging today no longer aligns with its long-standing industrial division of labor. On October 1, Applied Materials and Besi (BE Semiconductor Industries, Euronext code BESI) provided an institutional correction to this discrepancy in an official press release.
The conclusion is clear: hybrid bonding has evolved from a "materials engineering problem" confined to front-end fabs into a "full-process problem" requiring collaborative equipment solutions. The evidence chain begins six years ago and ends in a three-story building in Silicon Valley.
In 2020, the two companies jointly established a Hybrid Bonding Center of Excellence at Applied Materials' Advanced Packaging Development Center in Singapore. The division of labor was clear: Applied Materials contributed front-end capabilities such as etch, planarization, deposition, wafer cleaning, metrology, inspection, and particle defect control, while Besi provided die attach, interconnect, and assembly equipment. The most visible output of this six-year collaboration is the Kinex, the industry's first integrated die-to-wafer (D2W) hybrid bonding system, which for the first time integrated deposition and bonding processes into the same equipment process chamber logic.
Why was this collaboration indispensable? Hybrid bonding requires direct copper-to-copper connection, meaning the bonding surface must undergo deposition, planarization, and cleaning to near-wafer-level cleanliness; any single particle can ruin the entire bonding interface. Meanwhile, the final alignment of the copper pads is completed by the bonder. Front-end cleanliness management and back-end motion control are both essential; procuring equipment from two separate vendors and assembling the line shifts all integration risks to the customer.
According to the joint announcement on October 1, Besi joined Applied Materials' EPIC Center in Silicon Valley as an "Innovation Partner." This equipment and process innovation and commercialization center, with an investment of approximately $5 billion (capital expenditure phased in as customer projects are realized), is touted as the largest single investment in semiconductor equipment and process R&D in U.S. history, with operational readiness expected by 2026. Its three-story structure itself is a statement: cleanrooms are on the top floor, the subfab driving the equipment is in the middle, and supporting systems are at the bottom—physically inverting the R&D sequence to "cleanroom first."
After Besi engineers moved in, the joint development roadmap expanded to four items: a next-generation die-to-wafer hybrid bonding platform, scaling of thermal compression bonding (TCB) and its surrounding process ecosystem, a new die-on-panel integration platform beyond die-to-wafer and die-to-die, and optical interconnect applications supporting co-packaged optics (CPO). Prabu Raja, president of Applied Materials' Semiconductor Products Group, was blunt in the press release: advanced packaging is no longer a back-end assembly step; it is a materials engineering challenge requiring the same precision and cleanliness as front-end wafer fabrication.
2020
Establishment of the Singapore Center of Excellence
Investment scale for the EPIC Center
4 Items
Joint development roadmap
The three figures above represent: the year the partnership began, the planned investment for Applied Materials' EPIC Center in Silicon Valley (officially noted as to be phased in with customer projects), and the number of joint development directions announced following the expanded collaboration.
On the surface, this is a抱团 of two equipment makers, but the actual buying logic rests on the customer's timeline. Previously, building a hybrid bonding line required purchasing from both vendors separately and performing process integration in-house, a cycle measured in years. Now, deposition, cleaning, metrology, and bonding are pre-integrated in the same R&D environment. The vendors claim this allows customers to "access a fully co-optimized packaging process earlier." For memory fabs scaling HBM4 stack layers and logic fabs building 3D ICs, the most expensive trial-and-error phase of process debugging has been moved upstream to the equipment vendors' test lines.
There is a deeper industry implication: this is the first time the equipment industry has established a fixed "resident seat" arrangement where packaging bonding engineers are embedded in a front-end equipment vendor's R&D center. Prior collaborations were largely project-based—initiate, develop, deliver, disband. The EPIC innovation partner model turns Besi engineers into permanent residents, aligning both parties on the same process roadmap. Besi CEO Richard Blickman defined this seat's positioning in his own words: sitting at the same table as leading logic, memory, and system companies.
The inclusion of optical interconnects in the roadmap also warrants separate attention. The prerequisite for co-packaged optics is precisely the class of problem hybrid bonding solves: optical components and compute chips must be bonded with sub-micron precision, with interface cleanliness requirements matching wafer fabrication. Placing optical interconnects on the extension of bonding collaboration is an admission that CPO's bottleneck lies on the packaging process side. Applied Materials also disclosed that the University of California, Berkeley, has joined the EPIC Center's research collaboration, signaling that the center is evolving from a single company's R&D facility into a scheduling hub for the entire equipment ecosystem.
The author makes a judgment: within three years, die-on-panel will shift from an R&D checklist item to a standard option on panel-level packaging production lines. The area utilization benefits of larger panel formats can only be fully realized after bonding and front-end processes are coordinated. The falsification condition is clear: if, by the end of 2028, major OSATs' panel-level lines still rely primarily on reworked wafer processes and none have integrated die-on-panel equipment, this judgment is void.
The boundaries of equipment manufacturers are being redrawn. The next company to secure an EPIC seat will be a metrology firm, a lithography tool maker, or someone else entirely. It is worth noting today's date to look back later.