Everspin demonstrated a CXL-connected MRAM system at SNIA SDC 2026, targeting checkpointing and persistent KV caches to reduce GPU idle time.
The term "memory wall" has become overused. The real bottleneck for accelerators is often not raw memory speed, but the inability to perform any work while waiting for data—especially when systems must flush intermediate states to disk or retrieve cached data from flash, where wait times can reach milliseconds.
On September 29, Everspin Technologies demonstrated a system at the SNIA Developer Conference (SDC 2026) that connects its PERSYST MRAM to servers via a CXL interface, functioning as persistent memory with memory semantics. The company claims this is the world's first CXL-connected MRAM platform and is ready for customers to run their own workloads to measure performance gains.
Layer One: Where It Fits
The storage hierarchy is well understood: DRAM is fast but volatile, while NAND is cheap but slow. MRAM sits precisely in between—it retains data without power and offers access speeds close to memory. By connecting this layer to CXL, the demonstration provides it with a standard interface.
The system configuration is specific: a Supermicro AS-1116CS-TN server with an AMD EPYC 9355 (32-core) processor, paired with an AMD Alveo U250 FPGA platform and a Wolley CXL controller. The memory side uses an Everspin PERSYST 1GB DDR4 MRAM UDIMM. This combination provides cache-line-level, nanosecond access speeds, with write speeds 100 times faster than NAND-based solid-state storage.
100x
Faster writes than NAND solid-state storage
1GB
Capacity per module
Time serving data center customers
These three figures illustrate the system's position, scale, and heritage: write speeds are 100 times faster than NAND solid-state storage; the module capacity used in the demonstration is 1GB, placing it in the cache tier; and Everspin cites 15 years of collaboration with data center customers as the foundation for pushing MRAM into general-purpose computing platforms.
Layer Two: Who Needs It Most
The first batch of officially cited use cases includes checkpoints, persistent key-value caches, write buffers, and persistent caches. While these terms sound low-level, they all address the same type of overhead: the system must pause to flush data to prevent loss.
Consider checkpoints in training: long-running tasks require periodic saving of intermediate states. Writing to remote storage extends the overall task duration. If this layer is replaced with nanosecond-level persistent memory, the pause during the save operation is significantly reduced. Key-value caches face a similar issue—inference services store KV caches in DRAM, which has limited capacity and is volatile. When capacity is exceeded, the system must fall back to slower storage tiers.
Another capability often overlooked in configuration is CXL’s ability to pool and share memory resources across multiple hosts, allowing persistent memory capacity to be allocated to workloads that truly need it. For rack-level deployments, this is more significant than increasing single-node capacity—idle machines can lend their memory to busy ones. Why adopt the CXL standard interface?
Before CXL, integrating persistent memory into general-purpose servers required proprietary solutions: either dedicated memory channels or batteries to keep DRAM alive. CXL turns this into a standard operation—any device supporting CXL can be recognized and used with memory semantics by mainstream server platforms. For a company developing a new storage medium, interface standardization means customers can validate the technology without modifying their platforms. This factor is more critical to adoption than raw specifications.
Layer 3: Stuck on Cost
Sanjeev Aggarwal, President and CEO of Everspin, stated that CXL provides a standard path to bring persistent MRAM to a broader range of compute platforms. With systems now available to run workloads, customers can measure the benefits themselves. Bernard Shung, Ph.D., CEO of Wolley, described the demonstration approach: connecting persistent MRAM to the compute environment via CXL, enabling direct use on existing platforms through memory semantics.
Everspin is not the only company placing MRAM in this segment, but it has another pillar outside the data center. On September 2, Everspin announced a partnership with Teledyne HiRel Semiconductors to use 256Mb PERSYST MRAM in mission-critical aerospace and defense systems. These scenarios inherently have high requirements for data persistence during power loss and higher tolerance for cost.
Here is a falsifiable judgment: the cost per unit of capacity for MRAM dictates that it will remain confined to caching and buffering in the near term, rather than replacing DRAM or solid-state drives. The rationale is straightforward: the module demonstrated in this instance offers only 1GB per stick, whereas server DRAM modules exceed that capacity by two orders of magnitude, serving fundamentally different workloads. This assessment would be invalidated if a general-purpose server product line featuring MRAM as primary memory emerges before 2028.
This judgment leaves a significant window of opportunity for the industry. Both checkpointing and KV caching represent tangible financial losses in AI clusters; as long as unit costs continue to decline, demand for this layer will organically expand.
If your cluster contains data that must persist through power outages yet cannot tolerate latency, will you wait for this layer to mature, or will you first reduce the frequency of disk writes at the software layer? The capital expenditures for these two paths fall under entirely different budget lines.