The internal structure of an AI accelerator chip simplifies to three components: a central compute die, adjacent HBM stacks, and a silicon interposer connecting them. The first two determine speed, while the third dictates assembly, thermal management, and mass-production stability.
On September 29, JCET signed a contract in Wuxi for its high-end advanced packaging project. Invested by its wholly owned subsidiary, Jiangyin JCET Advanced Packaging Co., Ltd., the project focuses on the R&D and industrialization of silicon interposer 2.5D advanced packaging, while tackling 3D stacking and system-level integration for AI and high-performance computing markets. Wuxi Municipal Party Secretary Jiang Feng, Acting Mayor Cai Jianfeng, and JCET Director and CEO Zheng Li held talks and attended the signing ceremony.
A silicon interposer, also known as a silicon interconnect, is a high-density connection board fabricated using semiconductor processes, featuring micron-level routing and through-silicon vias (TSVs). Compute dies and HBM stacks are mounted on its surface, exchanging signals through the interposer before connecting to the motherboard via the underlying package substrate.
It is distinct from common organic substrates. While organic substrates struggle to achieve micron-level line widths and spacing, the interconnects between compute dies and HBM require thousands of parallel traces with sub-micron line widths, achievable only via semiconductor processes on silicon wafers. The trade-off is higher cost and limited area; the size of the silicon interposer directly determines how many HBM stacks a chip can support.
Consequently, the silicon interposer occupies an unglamorous yet critical position in the AI chip supply chain. It bridges advanced-process logic dies and HBM memory stacks while belonging to the packaging segment. Whoever masters this layer secures a stable position in the advanced packaging chain.
HPC Packaging Platform Capacity Expansion Investment
Power Module Packaging Upgrade Investment
HPC Project Construction Period
These figures come from JCET's private placement plan disclosed on the evening of September 3. The company plans to raise no more than 6.5 billion yuan, with 2.351 billion yuan allocated to a capacity expansion project for a high-performance computing advanced packaging platform, of which 1.5 billion yuan will be funded by the raised capital. The project is located at No. 1 Dong'an Road, Jiangyin City, with a construction period of 20 months. A separate project to upgrade advanced packaging and testing capacity for high-end power modules has a total investment of 1.636 billion yuan. It is important to distinguish that the new project signed on September 29 did not disclose an investment amount; these are two distinct matters.
JCET's relationship with Wuxi dates back a long way. The company's predecessor was the Jiangyin Transistor Factory, established in 1972, which was restructured into Jiangsu JCET Technology Co., Ltd. in 2000. Today, its manufacturing base and R&D layout remain centered on Wuxi. Since the start of the "14th Five-Year Plan," high-end smart manufacturing projects such as JCET Microelectronics and the Qixin Project have been implemented sequentially. The current silicon interposer project is an extension of this same trajectory.
The timing of the move in late September is also significant. The gap between the private placement plan and the project signing was only 26 days, indicating that funding arrangements and capacity planning are advancing in parallel. Major investments in the packaging and testing segment rarely materialize from a single contract alone; typically, funding sources must be secured first, followed by locking in land and supporting infrastructure, before equipment procurement and factory construction can begin.
Alongside this industrialization project, the Jiangsu Provincial Key Laboratory of High-Density Optical and Electrical Micro-System Integration was also announced. It is one of the province's first batch of enterprise-led provincial key laboratories (in preparation), led by JCET and jointly built with Southeast University and JCET Microelectronics. The research directions include high-density electrical micro-system integration, CPO (co-packaged optics), and energy-thermal collaborative management for high-power micro-systems.
These three developments point to the same conclusion: as computing clusters continue to expand, the headroom for traditional electrical interconnects in terms of bandwidth and power consumption is being exhausted. Bringing optical engines closer to compute and switch chips is a direction with clear benefits. The industrialization project addresses what can be delivered today, while the laboratory addresses whether there will be viable options three years from now. Deploying both tracks simultaneously is the aspect of this batch that warrants the most attention.
Here is a testable judgment: the true constraint on domestic 2.5D packaging capacity lies not in equipment, but in the yield of the silicon interposers themselves and their large-size exposure capabilities. The rationale is that silicon interposer areas are pushing toward the limits of photomasks. As area increases, the cost of scrapping an entire board due to a single defect becomes increasingly unsustainable, and this bottleneck cannot be solved by purchasing equipment. If, by 2027, the primary bottlenecks cited in publicly disclosed domestic 2.5D projects point to equipment delivery cycles while yield issues are rarely mentioned, this judgment will be proven wrong.
Another variable lies in the order structure. Once the silicon interposer production line is built, who will consume the capacity depends on the scheduling of domestic AI accelerator chips. A common risk in advanced packaging investment is that orders fail to keep pace with the newly built capacity.
If you were planning this production line, would you set capacity based on order volume or technology tier based on large-die yield? The direction these two curves take will determine whether the line is chasing demand or constrained by yield in two years.