The Huawei Mate 90 launched on October 1, shifting focus from pricing to a 1.5-micron bonding pitch revealed in third-party packaging cross-sections.
This is the bonding pitch for the Kirin 9050 Pro. Huawei stacks two layers of active circuits vertically, connected by high-density vertical interconnects with a 1.5-micron pitch, yielding approximately 500,000 interconnect points per square millimeter. Official disclosures cite 5 million total signal bonding points per chip and an inter-chip bandwidth of 125 TB/s.
Huawei itself coined the term "logic folding" for this approach. In May, He Tingbo, Huawei director and president of the semiconductor business unit, proposed the "Tau (τ) Law," shifting the optimization target from transistor size to signal transmission time. In a paper update, she used an analogy: a person's energy consumption on a workday comes not just from hours at the desk, but also from the significant energy spent commuting.
He Tingbo’s basis is that over 80% of energy consumption in an SoC module is spent on data movement. Traditional designs lay all circuits on a single plane, forcing signals to travel across the chip via wires hundreds of microns or longer. With folding, circuits are split into upper and lower layers, allowing signals to take vertical channels instead of long lateral paths.
Test data in the paper provides several benchmarks: typical core wire length is reduced by about 20%, with some critical paths shortened by up to 70%; clock routing for a specific processing module is reduced by 28%, and the number of clock buffers drops from 43,600 to 19,000. At equivalent performance levels, NPU power consumption decreases by 66%, GPU by 58%, and CPU performance cores by 41%.
+55%
Transistor Density Increase
-66%
NPU Power at Same Performance
1.5μm
Bonding Pitch
These three figures correspond to the increase in transistor density (from approximately 155 million to 238 million per square millimeter), the reduction in NPU power consumption at the same compute level, and the pitch precision of bonding points between the two circuit layers. A smaller value for the third metric allows for denser vertical interconnects.
The industry offers two interpretations of this path. One view sees it as a transitional solution to equipment restrictions, noting that it consumes more silicon area per chip and that stacking processes lengthen workflows and lower yields, making it unsustainable at scale. The other view considers it a viable long-term architectural route: as the benefits of transistor size scaling diminish year by year, signal latency will eventually become a harder ceiling than density, and early adoption yields early benefits.
I lean toward the latter interpretation, but it holds only if yields clear the threshold. Huawei’s own data embeds this premise: the folded design requires more silicon area than a flat one, and stacking adds manufacturing steps. Yu Chengdong, Huawei’s executive director and chairman of the Terminal BG, publicly admitted in late September that domestic advanced semiconductor capacity remains “extremely limited,” with Ascend AI accelerators and mobile chips competing for the same scarce wafer supply. Three key differences from flat designs
First, area: the same functionality requires more silicon area, raising unit costs. Second, process: the addition of wafer-to-wafer hybrid bonding means a defect in any layer scrubs the entire die. Third, design methodology: digital, analog, and memory circuits must be rearranged in three-dimensional space, making verification efforts an order of magnitude larger than in the flat era.
Placing this path on a timeline clarifies the pace. In May 2026, He Tingbo proposed the tau law. On September 7, the Mate XT 2 tri-fold device launched as the first commercial product featuring the Kirin 9050 Pro, the first commercial logic-folded chip. On October 1, the Mate 90 series debuted; only the Pro Max utilizes the logic-folded version, while the Mate 90 and Pro models feature the Kirin 9030 and Kirin 9035, respectively.
This tiering is itself informative. Huawei places its most expensive and complex solution in its top-tier models first, allowing users willing to pay a premium to absorb early-stage costs while yields scale up. The Mate 90 series starts at 5,999 yuan, while the Pro Max Collector’s Edition is priced at 10,999 yuan; the price gap between these two tiers precisely covers this cost differential.
My assessment is that the true bottleneck for logic folding right now is yield and wafer area, not the architecture itself. The architectural principles have already been proven by the product; what remains are purely engineering and cost issues. If Huawei deploys this solution in mid-range phones or tablets by the first half of 2027, it indicates that both hurdles have been cleared, invalidating my assessment. If a year passes and it remains exclusive to the top-tier model, it suggests the area and yield calculations have not yet balanced.
Another possibility is that capacity constraints override everything else. Since the design requires more wafer area and capacity is diverted to AI accelerators, consumer electronics scheduling must yield when both lines are under simultaneous strain.
If you were planning Huawei’s product roadmap, would you dare place logic folding in the 3,000-yuan price bracket next year? The area and yield calculations must be balanced on flagship devices first, or should capacity expansion directly dilute the costs? Choosing the wrong path between these two options would push the timeline back by a year.