The same batch of large interposers fits nine on a circular wafer but sixteen on a square panel. The difference is not just seven units, but whether the production line is economically viable.
Imagine a 5.5 reticle-size interposer as a desktop-sized sheet. On a 300 mm circular wafer, at most nine sheets fit, with the curved edges representing pure waste. On a 310 mm square substrate, the same sheet fits sixteen times; the extra seven come from the shape itself, not process advancement.
In late May this year, OSAT ASE implemented this shape shift on the production line. The company announced the industry's first automated 310 mm × 310 mm Panel-Level Packaging line, compatible with its FOCoS and FOCoS-Bridge fan-out packaging platforms. The official English page cites Q1 2027 for production start, while the Chinese press release states mass production in H1 2027.
Effective area per panel
Large interposer placement ratio
2/2 µm
FOCoS line width/space
These three figures represent the effective area of a single 310 × 310 mm panel, the ratio of large interposer placements on the panel versus a 300 mm wafer, and the line width/space capability on FOCoS (8/8 µm for FOCoS-Bridge). The placement ratio is the economic rationale for the line, while line width/space determines the tier of products it can support.
ASE’s official explanation states the pain point directly: interposer sizes are increasing, while wafer-level packaging efficiency is declining. These are two sides of the same coin—individual chip packaging areas are growing, while the edge utilization of circular carriers is fixed, meaning larger chips result in higher waste percentages.
Panel-Level Packaging solves this geometric problem. Switching from circular to square increases usable area, allowing more chips per processing cycle and improving material utilization. ASE cites AI accelerators, high-performance computing, network equipment, high-end gaming, and edge AI as target scenarios, all of which are packing more system functionality into the package, where area growth is outpacing what process miniaturization can compress.
One point worth noting is ASE's framing of its own position: panel-level packaging should not be viewed as a binary choice between panels and wafers, nor as a route conflict between OSATs and foundries. Wafer-level processing remains the most suitable option for many applications; the two are complementary. This statement is less an act of humility and more a reassurance to customers—products already designed for wafer-level processes do not need to be redesigned because of this new line.
Also centered on panel-level packaging, another thread is advancing in the industry: replacing organic substrates with glass. Last month, several glass manufacturers sequentially added 510×515 mm to their specification sheets, reflecting a convergence in dimensions around 'the next material for packaging.' Targets and timelines are still being set for around 2028.
What distinguishes the 310 mm tier is that it did not wait for material finalization. ASE selected a format compatible with existing carriers and design rules, with production line capabilities directly benchmarked against existing fan-out platforms: FOCoS supports down to 2/2 micron line width/spacing, FOCoS-Bridge supports down to 8/8 microns, and design rules remain consistent between wafer-level and panel-level. The trade-off in this path is clear—no pursuit of maximum format, but a priority on 'immediately accommodating today's designs.'
This event can be read in two ways. One view sees it as an inevitable upgrade from circular to square packaging, where early line construction secures a strategic position. The other is cooler: 310 mm is a transitional format chosen to fit existing equipment and carrier sizes, meaning today's lines may need another round of modifications once larger glass panel solutions mature. These two readings are not mutually exclusive; they jointly illustrate that the deployment speed of equipment and production lines is outpacing consensus on materials and processes.
Scaling up the format is not difficult; the challenge is keeping the large panel compliant throughout the process. ASE's own capability list, beyond fine-pitch interconnect and redistribution layers, includes materials, lithography, warpage, and process uniformity—warpage being the most typical enemy of panel-level packaging. The larger the substrate area, the more pronounced stress accumulation during thermal processing, making it harder to maintain alignment accuracy across the entire panel.
This is also why the line will not come online until 2027. Automated lines solve repeatability and throughput issues, but yield and warpage control require process windows to be worked out organically; they cannot be brute-forced with equipment. From this perspective, before 2028, yield and warpage will limit the volume ramp of panel-level packaging; format size is secondary. This judgment has a clear falsification method: if, before then, a manufacturer explicitly delays mass production due to 'insufficient format size,' it would indicate the direction was misread.
See you in the comments section. Once this line is running in Q1 next year, the first public yield data will likely say more about how far panel-level packaging has come than any size marketing.