Renesas released the TP65H020G4PLSGBD 650V GaN device, featuring 20mΩ on-resistance and an 8mm×8mm dual-side cooling PQFN package. The company claims it is the industry's first 650V dual-side cooling GaN for megawatt-scale AI data centers, with samples shipping to major OEMs and ODMs and mass production targeted for mid-2027.
The immediate reaction to such a release is often that the package has shrunk. But for power engineers, the only question that truly matters is: which segment of thermal resistance does dual-side cooling actually reduce, and is that reduction worth a 57% decrease in package size?
The surge in interest for 650V GaN stems from rack power scaling toward the megawatt level. According to Renesas' press release, single-rack power is climbing from approximately 120kW to the megawatt range. Power architectures are shifting from traditional low-voltage busbars to 800V high-voltage DC (HVDC), requiring an intermediate bus converter (IBC) to step down 800V to 48V, 12V, or 6V, while also covering battery backup units (BBU) and capacitor banks (CBU) in sidecar power cabinets.
GaN die area is significantly smaller than that of silicon MOSFETs with equivalent on-resistance. This advantage allows for lower parasitic capacitance and higher MHz switching frequencies, but the trade-off is higher heat dissipation per unit area under the same power load. Traditional top-cooling packages (TOLT, or standard PQFN) rely on a single primary thermal path: heat from the die travels to the top surface, through the top pad and thermal interface material (TIM), to the heat sink. The bottom pad primarily handles electrical connection and mechanical fixation, not primary heat dissipation.
When device power levels were low, a single heat path was not a bottleneck. As per-device current and switching frequency rise, this segment becomes the hardest constraint in the series thermal resistance. To gain more heat-dissipation area, the only option in the past was to enlarge the package. Renesas' previous-generation TOLT package measured 10mm×15mm, with an area of 150mm²; an 8mm×8mm PQFN is only 64mm², a 57% difference. This logic essentially trades area for thermal performance.
DSC creates a heat-dissipation path on the top surface of the package, allowing die heat to escape from both the top and bottom simultaneously. With two parallel paths, the equivalent thermal resistance drops. Renesas provides a conservative quantification: top-side thermal impedance is reduced by approximately 10%.
A 10% reduction may not seem dramatic, but its value lies elsewhere—board area. Once heat dissipation shifts from single-sided to dual-sided, the power that can be removed per unit area increases, allowing the package to shrink from 150mm² to 64mm². This 57% saving directly translates, in megawatt-scale racks, to whether an additional level of IBC can be fitted, whether busbar loops can be shorter, and whether more symmetric layouts between FETs are possible. One detail validated by Renesas is that the smaller package frees up PCB space, improving layout matching between devices.
It is also worth noting that dual-sided cooling is a mature engineering technique. Automotive-grade SiC modules have used dual-sided water cooling for years, with consistent structural concepts. The shift for GaN lies in the application scenario—moving this mechanism from large modules into 8mm×8mm small packages to serve IBCs in 800V HVDC systems, as well as BBU and CBU positions in sidecar power cabinets. Additionally, this device adheres to the industry-standard PQFN size, co-defined by Renesas and major AI infrastructure customers, with the aim of providing multiple sourcing options for procurement.
On-resistance
Reduction in board area
2.6
kW/in³ power density
The three figures above: 20mΩ is the on-resistance of this device in the 650V class, which Renesas claims is among the lowest in that category; 57% is the reduction in board area for the 8mm×8mm PQFN compared to the 10mm×15mm TOLT; and 2.6kW/in³ is the measured power density of a 6kW, 800V-to-48V LLC DC transformer (DCX) reference design built by Renesas using this device, controlled by its own RA6T3 MCU.
The same reference design yields another figure: module-level full-load efficiency is 0.21 percentage points higher than a circuit board using an equivalent TOLT package. Some may use this to argue that dual-sided cooling is 'just so-so'.
That conclusion is only half right. The LLC DC-DC converter stepping down from 800V to 48V already operates at high efficiency, leaving little room for improvement; a 0.21 percentage point gain at full load is not negligible. More importantly, the value of improved thermal resistance rarely shows up on the efficiency curve. It manifests in two ways: higher current capability at the same package size and lower junction temperature at the same current. The former determines how much power a single IBC can handle, while the latter dictates derating margins and lifespan. Engineers value this practicality: pushing up power without redesigning the board or adding extra cooling hardware is more valuable than a 0.2-point efficiency bump. In-depth industry analysis
Double-sided cooling is not cost-free for the system. Extracting heat from the top of the package means cold plates or heat sinks must be mounted directly above it, requiring redesign of TIM materials, assembly flatness, and clamping force. Better device-level thermal performance does not equate to simpler system-level thermal management. This is why Renesas repeatedly emphasizes maintaining the standard PQFN footprint and bundles the auxiliary power controller, gate driver, and MCU together. The barrier to entry is the complete power solution, not a single component.
The timeline makes this clearer. Renesas announced the device on September 30 and will exhibit it alongside its 800V power solution at the OCP Global Summit in San Jose, USA, from October 12 to 15. Currently, the device is in sample stage, with mass production scheduled for mid-2027. That leaves a gap of a year and a half between announcement and large-scale availability.
Here is a debatable judgment: the ultimate value of this device depends on when 800V HVDC truly scales; packaging is merely the entry ticket. If by 2027, 800V racks are still limited to a few pilots, the practical application of this 650V GaN device will be squeezed into local replacements in 400V or 800V-to-48V/12V IBCs, where its 57% board area advantage is worth only a 'space-saving alternative.' Conversely, once 800V becomes mainstream, suppliers who secure the standard PQFN footprint while holding the full stack of controllers, drivers, and MCUs will have far greater pricing power than those selling a single GaN device. Renesas is betting on the latter, but it is too early to verify this judgment until mid-2027.
If you are currently selecting components for an 800V IBC: will you shift your design toward double-sided cooling now to capture that 57% board area savings, or wait until mass production in mid-2027 when pricing and supply stabilize before switching?