A joint development pact between an equipment maker and a memory vendor usually signals either mature processes requiring customization or unresolved process windows. Kioxia's entry into Applied Materials' EPIC center falls into the latter category.
On September 29, Applied Materials announced from Santa Clara that flash memory maker Kioxia will join its EPIC center in Silicon Valley as an innovation partner. The two companies will co-develop next-generation storage technologies and 3D stacking structures for the AI era.
According to the announcement, the collaboration focuses on four areas: advanced memory cells and structures for AI applications, multi-chip stacking architectures for next-generation memory, advanced packaging to enhance interconnect performance in stacked chips, and materials engineering to support mass production. Three of these four areas involve structure, packaging, and materials, with only one directly related to the equipment itself.
332 layers
Current 3D NAND stacking layer count
Approx. 40nm
Word line layer vertical pitch
EPIC Center investment scale
These three figures represent the current 3D NAND stacking layer count, the vertical pitch between word line conductive layers, and the total investment in this joint R&D center. The third figure underscores the significance of the partnership, marking the largest investment to date in semiconductor equipment R&D in the United States.
3D NAND increases capacity by stacking vertically: piling memory cells layer upon layer, where more layers mean greater capacity per unit area. This approach has been pursued for years, but each additional layer squeezes the remaining physical margin.
The bottleneck lies in the vertical pitch between word line conductive layers. Public technical analyses indicate this pitch is approximately 40 nanometers in current advanced products. At this scale, the thin film stack that actually stores charge—a silicon oxide, silicon nitride, silicon oxide sandwich structure—begins to interfere with adjacent cells. Simultaneously, the selectivity of the etch process used to define the structure decreases, meaning it is difficult to etch one layer without damaging the layer below.
To further reduce the pitch and support more layers, a new set of materials is required: new dielectrics that can fill uniformly in gaps below 40 nanometers, word line metal fills with lower resistivity, and new etch chemistries capable of precisely distinguishing adjacent materials. These three items fall squarely within the equipment maker's product lines: chemical vapor deposition, physical vapor deposition, and atomic layer deposition tools.
Material and process compatibility cannot be developed in isolation for this type of structure. Equipment makers cannot independently develop the appropriate material processes because they do not know how customers will actually configure their stacks; memory makers cannot independently optimize the stack because the formulations and equipment parameters are held by the equipment vendors. The traditional buyer-seller relationship creates a bottleneck for both sides in this process.
The design of the EPIC Center is intended to resolve this misalignment. According to Applied Materials, the center compresses the cycle from early research to mass production, allowing customers to engage during the R&D phase of materials and equipment rather than waiting until the equipment is finalized to submit requirements. This early involvement offers direct value to memory makers: participating while the process window is still being tuned is far more cost-effective than modifying equipment after the fact.
Kioxia also brings a structural advantage. Its CBA (CMOS and Array Bonding) architecture moves the peripheral CMOS circuits from the edge of the memory array to underneath the array, freeing up the edge space to increase the effective number of layers. This allows density improvements to be pursued in two directions: vertically through pitch reduction and laterally through the relocation of peripheral circuits.
Viewed over a longer timeline, this addition is the final step in a series of moves. Samsung Electronics joined as a founding partner in February 2026, SK hynix and Micron joined in March, TSMC joined in May, and Kioxia completed the group on September 29. For the first time, four major memory manufacturers are now part of the same joint R&D system.
According to reports, the EPIC Center involves more than ten participants, including fabs, chip design companies, equipment partners, and universities; R&D equipment is being moved into the cleanroom, and the opening ceremony is scheduled for October 12. The center is only just about to officially open.
A testable judgment can be made: before 2028, 3D stacking will not form a standardized equipment platform and will remain in the form of customer-specific customization. The test is clear—if multiple memory makers share the same standardized stacking equipment solution before 2028, it indicates that the process window has converged, and this judgment would be invalid. The fact that four manufacturers currently need to sit in the same R&D center to tune processes with equipment makers is itself evidence that the window has not yet converged.
See you in the comments. The next point of observation lies in the form of equipment orders—when orders shift from 'general-purpose machines' to 'customer-specific configurations,' process divergence will appear in the quotes.