Ensuring Excellent Mobile Connectivity for...

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Organised by the School of Electrical and Electronic Engineering and supported by semiconductor firm EnSilica and a number of industry sponsors, the initiative used the Tiny Tapeout framework to deliver practical ASIC design experience. The approach, which uses a multi-project wafer (MPW) model, enables multiple designs to be manufactured together at reduced cost.According to organisers, the event

The development of next-generation server memory DDR6 is reportedly entering early hardware validation, as memory makers and supply chain partners begin pre-development work ahead of formal standardization. The industry is coordinating closely across chip designers, substrate manufacturers, and controller IP providers to prepare for the transition from DDR5, which is now entering maturity in data

Intel is gaining momentum in both chip design and foundry operations. Its PC platform roadmap for the next two years is coming into sharper focus as process technology and yield improve, according to PC supply-chain sources.

Demand for faster design and more automation grows from key customers.

Full automation is still a goal, but humans will still be in the loop for the foreseeab...