Cadence and Intel deepen partnership to prepare Intel 14A for next-generation chip designs - Tech Critter

Cadence and Intel Foundry have deepened their multi-year partnership to accelerate the development of next-generation chip designs on Intel's 14A process node. The collaboration leverages Cadence’s AI... Read original →

Intel and Cadence’s deepened 14A collaboration marks a strategic pivot toward AI-driven DTCO as the new foundation for sub-2nm design. Technically, this forces EDA-PDK co-development into mainstream workflows, pressuring rivals like Synopsys to accelerate AI integration while pulling advanced packaging (e.g., ChipStack) into early process validation. On compliance, tightening U.S. export controls compel Intel Foundry to decouple its PDKs from restricted IP—raising barriers for non-U.S. foundries like Samsung. In response, TSMC (Taiwan, China) may double down on its closed-loop InFO-3D + EDA ecosystem, while SMIC (Shanghai, China) risks falling behind in DTCO maturity. Within 18 months, the industry will hit an inflection point: process leadership will be defined not by transistor density alone, but by who owns the end-to-end co-optimization stack from AI algorithms to EUV patterning.