Semiconductor News & Analysis Feed
17 articles
2026-05-27
semiengineering.com
2026-05-27
Semiconductor Engineering
Combining manufacturing-resolution geometry with deterministic, solver-accurate computation changes the economics of thermal analysis for advanced 2.5D packages.
Thermal management has become the defining bottleneck in high-performance computing (HPC) and AI accelerator packaging.
Modern packages integrate high-power ASICs with multiple High Bandwidth Memory (HBM) stacks on a silicon interposer,
2026-05-27
semiengineering.com
2026-05-27
Semiconductor Engineering
Researchers from Micron Technology and Argonne National Laboratory have released “Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles”.
Abstract
“The transition from standard generative AI to reasoning-centric architectures, exemplified by models capable of extensive Chain-of-Thought (CoT) processing, marks a fundamental paradigm shift in system requireme
2026-05-26
semiengineering.com
2026-05-26
Semiconductor Engineering
Researchers from Grenoble INP – UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”.
Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and performance, t
2026-05-22
semiengineering.com
2026-05-22
Semiconductor Engineering
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2026-05-21
semiengineering.com
2026-05-21
Semiconductor Engineering
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2026-05-21
semiengineering.com
2026-05-21
Semiconductor Engineering
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2026-05-21
semiengineering.com
2026-05-21
Semiconductor Engineering
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2026-05-21
semiengineering.com
2026-05-21
Semiconductor Engineering
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2026-05-19
semiengineering.com
2026-05-19
Semiconductor Engineering
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2026-05-14
semiengineering.com
2026-05-14
Semiconductor Engineering
Key Takeaways:Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability.Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out.AI is beginning to
2026-05-12
semiengineering.com
2026-05-12
Semiconductor Engineering
A new technical paper, “CMOS-compatible ferroelectric tunnel junctions integrate stochastic sampling and deterministic computing for image generation,” was published by researchers at Seoul National University, Sungkyunkwan University, Hanyang University, Sogang University, and SK Hynix.Abstract“Recent progress in generative modeling has intensified the need for compact, energy-efficient hardware
2026-05-12
news.google.com
2026-05-12
Semiconductor Engineering
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2026-05-12
semiengineering.com
2026-05-12
Semiconductor Engineering
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2026-05-11
semiengineering.com
2026-05-11
Semiconductor Engineering
New technical papers recently added to Semiconductor Engineering’s library:Technical PaperResearch OrganizationsSource-position-dependent transmission cross coefficient formula including polarization and mask three-dimensional effects in High NA EUV🔗Science TokyoPerformance and Energy Benefits of MRDIMMs🔗Barcelona Supercomputing Center,UPC,Micron,IntelEnergAIzer: Fast and Accurate GPU Power Estima
2026-05-07
semiengineering.com
2026-05-07
Semiconductor Engineering
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Securing Chiplet-Based Platforms: Dist
2026-05-06
semiengineering.com
2026-05-06
Semiconductor Engineering
A new technical paper, “AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving,” was published by researchers at UC San Diego, Columbia University, Yonsei University, NVIDIA, and Samsung.Abstract“All current LLM serving systems place the GPU at the center, from production-level attention-FFN disaggregation to NVIDIA’s Rubin GPU-LPU heterogeneous platform. Ev
2026-05-05
www.indexbox.io
2026-05-05
IndexBox