Observability Is A Missing Layer In AI-Era Chiplet Design - Semiconductor Engineering

As artificial intelligence becomes increasingly integrated into chip design, observability emerges as a critical requirement. In next-generation silicon, AI can interpret system behavior at scale, but... Read original →

AI-driven observability is evolving from an add-on to a foundational requirement in chiplet architectures, forcing a structural overhaul of the EDA stack. Upstream IP vendors must embed real-time telemetry interfaces, while downstream data centers rely on on-chip TinyML models for predictive maintenance, closing the design-deployment-feedback loop. Regulatory pressures—particularly the EU Chips Act and U.S. export controls—are compelling firms to localize observability data processing, increasing operational complexity and costs for multinational chipmakers. Cadence and Synopsys are rapidly integrating AI analytics engines, while smaller players like Arteris and Movellus focus on lightweight monitoring IP to avoid head-on competition. Within 18 months, chiplets with native observability will become a non-negotiable procurement criterion for cloud providers, compelling the entire supply chain to embed digital twin interfaces at the pre-silicon stage—not just a technical shift, but a realignment of ecosystem control.