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TSMC is accelerating CoWoS capacity expansion while also pushing ahead with next-generation panel-level packaging, CoPoS, aiming to use a new "round-to-square" architecture to break through cost and capacity bottlenecks in large AI chip packaging and build its next competitive moat.

The market for fan-out panel-level packaging(FOPLP) and glass substrate packaging is set to grow sharply as chipmakers race to support AI and high-performance computing. For global readers, the shift could shape future device performance, supply chains, and where advanced semiconductors are manufactured and assembled.

A South Korean media report claiming TSMC is preparing to launch panel-level packaging at mass-production scale as early as 2027 has drawn skepticism from Taiwan industry sources, who say the timeline is likely premature and that the company remains focused on evaluating multiple advanced-packaging options.

By Allen Lee Published: Jun 15 2026, 15:57 PM EDT Share on Facebook Share on Twitter Share on LinkedIn Share on Reddit Share on Flipboard Share on Pocket The TSMC logo is displayed at the Taiwan Semiconductor Manufacturing Company branch and Innovation Museum, highlighting the company branding and signage inside and outside the site in Hsinchu, Taiwan, January 27, 2026. JIMMY BEUNARDEAU/GETTY IMA

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Equipment maker Manz recently announced the successful delivery of the world's first 310mm x 310mm panel-level packaging (PLP) electrochemical deposition (ECD) mass-production tool, further expanding its footprint in advanced packaging process equipment and demonstrating integrated capabilities spanning in-house R&D, process and system integration, and mass-production deployment.

Linkotech said its fan-out panel-level packaging rollout is showing early momentum, with certification from a North American low-Earth-orbit satellite communications customer and first equipment deliveries completed in the first half of 2026. The company said related sales could quickly rise to double digits as a share of annual revenue, with implications for supply chains worldwide.

Generative AI, HPC, and large data centers are raising demand for chips with higher power efficiency, stronger thermal control, and denser packaging, making advanced packaging a more strategic part of the semiconductor supply chain. In China, panel-level packaging (PLP) is gaining traction for its larger format, higher output, and lower-cost potential.

Advanced Semiconductor Engineering (ASE) has unveiled its industry-first automated panel-level packaging (PLP) system, a development poised to reshape global artificial intelligence (AI) and high-performance computing supply chains by significantly improving chip integration speeds and manufacturing efficiency for AI data centers and cloud infrastructure providers.

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Hiwin Technologies and Qualcomm Inc. announced a partnership at Computex 2026 to integrate Qualcomm Dragonwing Q6 series processors into Hiwin's Load Port products, delivering edge AI capabilities for semiconductor panel-level packaging (PLP) equipment. The collaboration positions Hiwin's Load Port as the smart edge node in front-end modules, aiming to improve real-time image processing, status se