TSMC PLP timeline faces skepticism from Taiwan industry sources

If TSMC truly mass-produces panel-level packaging (PLP) by 2027, it would force substrate and equipment suppliers to accelerate compatibility—but with CoWoS capacity still tight, diverting resources risks internal conflicts among advanced packaging roadmaps. Taiwan, China’s supply chain remains skeptical due to PLP’s slow yield ramp, lack of material standardization, and high compliance costs under U.S. CHIPS Act incentives that favor front-end over back-end processes. Samsung and Intel will likely double down on FOPLP or EMIB to capture cost-sensitive HPC orders. Over the next 18 months, the industry will enter a ‘packaging arms race,’ yet the winner won’t necessarily be the first mover but the one integrating design-manufacturing-test data loops. TSMC’s timeline appears more as strategic signaling than an executable plan.