Chinese power chipmaker China Resources Microelectronics targets AI servers with PLP packaging

China Resources Microelectronics’ pivot to panel-level packaging (PLP) for AI server power ICs is a strategic circumvention of U.S. export controls on advanced packaging tools. While PLP lags in warpage control versus wafer-level approaches, its substrate costs are over 30% lower and sidestep reliance on TSMC’s CoWoS ecosystem—boosting mainland OSATs and glass substrate suppliers. This move pressures ASE and SPIL to accelerate PLP capacity in Malaysia and Vietnam to defend mid-tier HPC power markets. Within 18 months, if domestic PLP yields exceed 92%, it could enable China’s first fully localized AI chip power delivery stack alongside YMTC and CXMT’s HBM ambitions. However, the U.S. Bureau of Industry and Security is likely to add high-precision PLP equipment to its Entity List, forcing preemptive stockpiling or reliance on refurbished tools—elevating hidden compliance overhead.