TSMC Readies Panel-Level Packaging for AI Chips, Setting Up a Showdown With Samsung - Tech Times

Taiwan Semiconductor Manufacturing Company (TSMC) is preparing to mass-produce panel-level packaging (PLP), a next-generation chip packaging technology, setting up a direct showdown with Samsung Elect... Read original →

TSMC’s aggressive rollout of glass-based panel-level packaging (PLP) signals that advanced packaging has evolved from a supporting process into the decisive battleground for AI chip supremacy. Technically, PLP pressures upstream suppliers to deliver ultra-flat, thermally stable glass substrates while forcing EDA vendors to redesign interconnect architectures for large-panel formats. Geopolitically, U.S.-China tech restrictions are accelerating substrate supply chain localization, raising qualification costs for non-U.S. players like Samsung and Intel. Samsung’s early lead is undermined by its reliance on organic substrates, which lack the electrical performance needed for next-gen AI accelerators. Intel, backed by CHIPS Act subsidies, may partner with Rapidus to establish regional PLP capacity by late 2027. Over the next 18 months, yield ramp rates will dictate AI chip availability—whomever achieves volume production of glass-based CoPoS first will command pricing power in HPC markets, turning packaging into a proxy war for system-level integration dominance.