ASE launches first automated PLP line, eyes 1H27 production

ASE’s deployment of the industry’s first automated panel-level packaging (PLP) line in Kaohsiung, Taiwan, China, marks a strategic pivot beyond mere process improvement—it redefines AI chip manufacturing economics. Technically, PLP disrupts the ABF-substrate-dependent FC-BGA ecosystem by scaling wafer-level cost structures to large-panel formats, pressuring upstream material suppliers to deliver low-warpage glass carriers and high-resolution photoresists. Downstream, GPU makers like NVIDIA could bypass CoWoS bottlenecks. Geopolitically, volume production by 1H27 may coincide with tightened U.S. CHIPS Act subsidy criteria, inviting scrutiny over non-U.S. advanced packaging capacity and raising compliance overhead. Competitors—Amkor, JCET, and especially TSMC—will likely accelerate Fan-Out or InFO-PLP development to defend their 3D integration moats. Within 18 months, PLP will become the linchpin of substrate-less HPC packaging; whoever achieves >95% yield first will set the next-gen standard.