SMIC's third-gen 7nm node shows smaller metal pitch than Intel 18A, higher transistor density than TSMC N6 without EUV

Recent teardown analysis by SemiAnalysis of Huawei's Kirin 9030 chip revealed that SMIC's third-generation 7nm process (N+3) achieves a smaller metal pitch than Intel's 18A and surpasses TSMC's N6 in ... Read original →

SMIC’s N+3 process achieving higher transistor density than TSMC’s N6 without EUV is a feat of extreme DUV multi-patterning and DTCO—but at steep costs in yield, design complexity, and economics. This forces domestic EDA, IP, and packaging ecosystems to rapidly adapt to aggressive metal pitch constraints. U.S. export controls, ironically, have accelerated China’s non-EUV scaling ingenuity, yet this path lacks scalability beyond ~5nm. In response, TSMC may expedite N4P/N3E capacity outside Taiwan, China to reassure global clients, while Intel leverages 18A’s full-node maturity for foundry marketing. Over the next 12–24 months, SMIC’s advance will primarily serve strategic domestic clients like Huawei but won’t disrupt the high-end logic market—though it redefines what’s possible in mature-node performance extension.