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Unifying Software And Semiconductor Development - Semiconductor Engineering

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semiengineering.com 2026-07-08 Semiconductor Engineering

Photoluminescence Inspection Is Changing How Manufacturers Protect Yield In SiC And GaN Devices - Semiconductor Engineering

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semiengineering.com 2026-07-07 Semiconductor Engineering

Observability Is A Missing Layer In AI-Era Chiplet Design - Semiconductor Engineering

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semiengineering.com 2026-07-01 Semiconductor Engineering

In next-generation silicon, AI can interpret system behavior at scale, but only if observability is designed into the fabric as a first-class architectural capability. Experts At The Table: In-silicon observability—also known as on-die or on-chip visibility—is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor

chip design artificial intelligence observability on-chip data AI integration EDA tools data collection system reliability

Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna) - Semiconductor Engineering

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semiengineering.com 2026-06-30 Semiconductor Engineering

Researchers from ETH Zurich, lowRISC, and University of Bologna published a technical paper titled “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.” This paper describes Croc, an open-source, customizable RISC-V SoC platform and teaching flow that lets students take domain-specific chip-design projects from architecture and RTL through physical

RISC-V Open Source Chip Design Semiconductor Education SoC Platform RTL Design Physical Design Silicon Manufacturing

Rethinking Chip Verification - Semiconductor Engineering

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semiengineering.com 2026-06-29 Semiconductor Engineering

Specification engineering is gaining traction as a potential solution to the verification bottleneck. EDA vendors and their customers are looking at a different way to tackle the semiconductor verification bottleneck, combining AI with massive simulations to create a single reference point for designs. The goal is to reduce the time to sign off with better coverage and more confidence by leverag

chip verification EDA tools AI in semiconductor specification engineering design flow optimization chip design system-level design verification bottleneck

Wafer-Scale vs. Chiplets: The New War? Part 2 - Semiconductor Engineering

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semiengineering.com 2026-06-25 Semiconductor Engineering

In Part 1, we looked at the innovations underpinning the Cerebras WSE-3 and why its most significant breakthrough is the elimination of data movement overhead at the architectural level, not better yield management or thermal engineering. Cerebras’ on-wafer fabric is a viable answer to the question being asked by the entire industry: how do you move data fast enough that compute stops waiting? Th

Wafer-scale integration Chiplets Computing architecture Data movement bottleneck HBM stacking Interconnect topology Energy efficiency Heterogeneous integration

Executive Outlook: Agentic AI’s Impact On Chip Design - Semiconductor Engineering

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semiengineering.com 2026-06-25 Semiconductor Engineering

Can engineers trust AI to get everything right in semiconductor design and verification? Semiconductor Engineering sat down to discuss the pros and cons of using agentic AI in chip design and verification, with Cindy Cui, vice president of global customer success at ChipAgents; Wally Rhines, CEO of Silvaco; Shelly Henry, CEO of Moores Lab AI; Dave Kelf, CEO of Breker Verification Systems; Vince W

Agentic AI Chip Design EDA Industry Artificial Intelligence Semiconductor Manufacturing Chip Verification AI Tools Chip Development Process

Introducing An Agentic LLM For Chip Design - Semiconductor Engineering

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semiengineering.com 2026-06-25 Semiconductor Engineering

A fine-tuned model brings frontier-level AI performance to chip design. By Tanay Biradar, Surya Gunukula, Tengxiao Liu, and Kexun Zhang ChipAgents has introduced Renoir, an agentic large language model (LLM) whose name means “renew.” In early chip design benchmarks, Renoir outperforms the base model it was trained on and cuts costs by more than half. Furthermore, it can run entirely on-premises,

chip design AI large language model semiconductor industry AI chip LLM application chip design tools data security

Research Bits: June 23 - Semiconductor Engineering

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semiengineering.com 2026-06-23 Semiconductor Engineering

Redesigning high-NA EUV; embedded liquid cooling; light wavelength analysis. A researcher from the Okinawa Institute of Science and Technology (OIST) proposes redesigning the illumination systems and projectors used in high-NA EUV lithography to reduce optical effects and enhance resolution. In the proposed projector design, the collector mirrors in the illumination system have a simpler design

EUV lithography High NA Semiconductor manufacturing Liquid cooling Chip thermal management Optical wavelength analysis Nanofabrication Optical system design

Mask Economics Shape High-NA EUV Adoption - Semiconductor Engineering

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semiengineering.com 2026-06-22 Semiconductor Engineering

Rising mask costs, tighter high-NA requirements, and new materials challenges are forcing chipmakers to weigh litho choices against volume, design strategy, and total process cost. Experts at the table: Semiconductor Engineering sat down to discuss new mask technology challenges with Aki Fujimura, CEO at D2S; Glen Scheid, operations manager at Micron; Harry Levinson, principal lithographer at HJL

EUV Lithography Semiconductor Manufacturing Photomask Chip Design Manufacturing Cost High NA EUV Lithography Process Chip Industry Trends

Hydra Host Archives - Semiconductor Engineering

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news.google.com 2026-06-19 Semiconductor Engineering

P49 OASIS Archives - Semiconductor Engineering

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semiengineering.com 2026-06-18 Semiconductor Engineering

Skip to main content Enable accessibility for low vision Open the accessibility menu Submit SUBSCRIBE Chinese (Simplified) English HOME SYSTEMS & DESIGN LOW POWER - HIGH PERFORMANCE MANUFACTURING, PACKAGING & MATERIALS TEST, MEASUREMENT & ANALYTICS AUTO, SECURITY & EDGE AI SPECIAL REPORTS BUSINESS & STARTUPS JOBS KNOWLEDGE CENTER TECHNICAL PAPERS EVENTS & WEBINARS VIDEOS & RESEARCH NEWSLETTERS

Curvilinear Masks MULTIGON Mask Data Preparation Lithography Inverse Lithography Technology Optical Proximity Correction Semiconductor Manufacturing Mask Fabrication

Accelerating GAA Logic Yield Optimization With Digital Twins - Semiconductor Engineering

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semiengineering.com 2026-06-18 Semiconductor Engineering

As logic devices transition from FinFETs to more complex gate-all-around (GAA) architectures, manufacturing variability has become a major barrier to achieving high yield.1,2 Hundreds of tightly coupled process steps now contribute to yield loss, making traditional wafer-based optimization slow, expensive, and often limited to addressing one failure mode at a time.3,4,5 To overcome these challeng

GAA architecture FinFET transition Digital twin Yield optimization Semiconductor manufacturing Machine learning Process simulation Process parameter tuning

GaN Power Devices Go Vertical - Semiconductor Engineering

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semiengineering.com 2026-06-18 Semiconductor Engineering

Why new designs and process flows could help overcome manufacturing challenges. Gallium nitride power devices have made significant inroads into low-voltage applications like chargers for consumer electronics. High-voltage applications like power generation and transportation have more demanding requirements and have, so far, been more skeptical of GaN’s potential. Requirements for power devices

Gallium Nitride Power Devices Vertical Design Semiconductor Materials Wide Bandgap GaN-on-Silicon Power Management Device Reliability

Fault Injection Framework Targets RISC-V Security Weak Spots - Semiconductor Engineering

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semiengineering.com 2026-06-15 Semiconductor Engineering

Researchers from Politecnico di Torino and CEA-List published a technical paper titled “InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment.” “Fault Injection Attacks (FIAs) are a significant threat to hardware security, capable of compromising systems by inducing malicious faults in computation or storage. Evaluating resilience against such attacks is challenging due to th

RISC-V Hardware Security Fault Injection Attack Simulation Environment gem5 Vulnerability Assessment Computational Security Chip Design

Battery Booster Facility Archives - Semiconductor Engineering

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semiengineering.com 2026-06-12 Semiconductor Engineering

Skip to main content Enable accessibility for low vision Open the accessibility menu Submit SUBSCRIBE Chinese (Simplified) English HOME SYSTEMS & DESIGN LOW POWER - HIGH PERFORMANCE MANUFACTURING, PACKAGING & MATERIALS TEST, MEASUREMENT & ANALYTICS AUTO, SECURITY & EDGE AI SPECIAL REPORTS BUSINESS & STARTUPS JOBS KNOWLEDGE CENTER TECHNICAL PAPERS EVENTS & WEBINARS VIDEOS & RESEARCH NEWSLETTERS

Battery Technology Semiconductor Manufacturing Chip Design Advanced Packaging AI Infrastructure Memory Technology EUV Lithography Industry Trends

open AI models Archives - Semiconductor Engineering

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news.google.com 2026-06-12 Semiconductor Engineering

Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design - Semiconductor Engineering

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semiengineering.com 2026-06-11 Semiconductor Engineering

Energy-efficient SoC design, optimizing PPA, deep low-voltage operation, and advanced power management techniques. Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability acro

Foundation IP Chip Design Energy Efficiency SoC Low Power Design Power Management Advanced Process Semiconductor Technology

What I Learned At The 2026 GSA Tech Summit: The Future Of Semiconductor Collaboration Is Full Stack - Semiconductor Engineering

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semiengineering.com 2026-06-09 Semiconductor Engineering

Advanced node manufacturing and heterogeneous integration require partnerships that span the full value chain. I had the privilege of joining a panel at the Global Semiconductor Alliance (GSA) Tech Summit in June in Scottsdale, Arizona, titled “Collaboration Models That Actually Work.” It was a fitting title for an event that brought together executives from across the semiconductor ecosystem, i

Semiconductor Collaboration Full-Stack Collaboration Advanced Node Manufacturing Heterogeneous Integration Data Standardization AI in Manufacturing Chip Design and Manufacturing Supply Chain Integration

Chip Industry Week In Review - Semiconductor Engineering

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semiengineering.com 2026-06-05 Semiconductor Engineering

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon’s 1.5 micron L/S litho; IC market rises; Apple’s chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets. Fig. 2: WSTS forecast summary by region and product segment. Source WSTS Global |In-Depth |Reports and D

AI chips Semiconductor manufacturing Advanced packaging Wafer fabrication equipment Power semiconductors Quantum computing Chip design Data centers

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