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JEDEC finalized a new HBM4 packaging specification called SPHBM4 that aims to broaden high bandwidth memory (HBM) use cases by reducing packaging complexity and cost, industry sources reported. According to ET News, the DRAM subcommittee completed its review, and the JEDEC board gave final approval, positioning the standard to influence AI semiconductor cost structures and substrate choices.

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SPHBM4 is a new JEDEC standard that aims to solve the high cost and packaging concerns with existing HBM technologies. Almost all AI & HPC accelerators rolling out these days feature some form of HBM memory. The highest-end solutions are leveraging the latest HBM4 designs, and HBM4E is being sampled to the top chipmakers. But as demand continues to rise, and shortages persist in the premium DRAM

JEDEC has released two new guideline documents aimed at supporting the growing use of silicon carbide (SiC) power semiconductors in applications ranging from electric vehicles to industrial power systems. The publications, JEP203 and JEP204, were developed by the JC-70.2 Silicon Carbide Subcommittee and are available as free downloads from the JEDEC website.

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AP JEDEC® Releases New SiC Guidelines to Improve Reliability and Evaluation in Power Electronics Business Wire 9 hrs ago 0 Facebook Twitter Email Facebook Twitter Email Print Copy article link Save ARLINGTON, Va.--(BUSINESS WIRE)--Jun 3, 2026-- JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, announced the publication of JEP

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