JEDEC Approves SPHBM4 to Break HBM’s Costly Packaging Bottleneck, Retaining HBM4-level Speeds With Standard Packages - Wccftech

JEDEC has approved the SPHBM4 standard, a new specification designed to address the high cost and complex packaging challenges associated with current HBM technologies. By enabling HBM4-level performa... Read original →

JEDEC’s SPHBM4 standard marks a strategic pivot away from overreliance on costly advanced packaging in HBM ecosystems. By quadrupling signaling speeds and extending die-to-memory distance to 20mm, it delivers near-HBM4 performance using conventional packages—directly undermining the dominance of TSV and CoWoS processes. This benefits non-TSMC foundries and second-tier OSATs in Taiwan, China and Korea. From a compliance standpoint, reduced dependence on geopolitically sensitive substrates like high-end ABF enhances supply chain resilience amid U.S.-EU reshoring pushes. Samsung and SK Hynix will likely accelerate HBM4E adoption to preserve premium pricing, while NVIDIA may integrate SPHBM4 into mid-tier AI accelerators to curb BOM costs. Within 18 months, as glass substrates approach commercialization, SPHBM4 will become the linchpin for rebalancing performance and affordability in HPC, democratizing AI infrastructure access.