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Huawei's recent introduction of the LogicFolding chip design concept represents a strategic shift toward enhancing signal speed rather than shrinking transistor sizes, a move particularly significant amid U.S. sanctions on advanced semiconductor technologies. Based on the Tau Scaling Law, this appro

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool tailored for Huawei's LogicFolding architecture, a significant step toward domestic chip design autonomy. Unlike conventional 2D design approaches, this tool treats multi-layer chips as

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool tailored for Huawei's LogicFolding architecture, marking a significant step toward domestic chip design autonomy. Unlike conventional 2D design methods, this tool employs a true 3D appr

Huawei unveiled its novel 3D chip architecture, LogicFolding, at the IEEE International Symposium on Circuits and Systems, claiming it can achieve transistor density equivalent to 1.4nm processes by 2031 without access to advanced lithography tools. The technique folds traditional flat circuits into

On May 25, 2026, Huawei unveiled its novel chip architecture, 'LogicFolding,' at the IEEE ISCAS conference in Shanghai, aiming to bypass reliance on ASML's extreme ultraviolet (EUV) lithography machines. By stacking logic circuit layers in three dimensions, Huawei claims a 55% improvement in transis

Huawei has unveiled a breakthrough chip design technology aimed at overcoming U.S. sanctions, targeting 1.4nm-class chips by 2031. The innovation is based on a novel 'LogicFolding' architecture and a 'Tau Scaling Law' that replaces Moore's Law. By prioritizing signal speed over transistor miniaturiz