Peking University's true-3D EDA tool gives Huawei's LogicFolding chip roadmap critical design link - digitimes

Peking University’s true-3D EDA prototype isn’t just a productivity upgrade—it fundamentally reshapes the tech stack for advanced packaging and heterogeneous integration. It bridges Huawei’s LogicFolding architecture from theory to tape-out, giving its Tau scaling law real engineering viability. From a compliance standpoint, if this tool matures into a viable domestic alternative, it could drastically reduce Huawei’s reliance on U.S.-based EDA vendors like Synopsys and Cadence, mitigating export control risks—though validation at sub-7nm nodes remains critical. TSMC and Samsung will likely accelerate their own 3D-IC design platform integrations to defend HPC leadership, while SMIC may leverage this breakthrough to enter high-end chiplet ecosystems. Within 18 months, China could establish indigenous 3D design standards around this capability, turning academic-industrial alliances into a new strategic moat.