Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool tailored for Huawei's LogicFolding architecture, marking a significant step toward do... Read original →

Peking University’s LogicFolding-tailored 3D EDA tool represents an architectural bypass of EUV constraints. Its ripple effect will force upgrades in domestic packaging, thermal interfaces, and interconnect materials—conventional 2.5D interposers can’t support true vertical co-optimization. Compliance-wise, while lacking advanced-node PDKs, the tool sidesteps U.S.-controlled IP, reducing Huawei’s secondary sanction exposure. Global EDA giants like Cadence won’t open full 3D flows to Chinese firms; instead, they’ll deepen ties with Korean and Vietnamese foundries. Within 18 months, a critical gap may emerge between mainland China’s design ambitions and Taiwan, China’s manufacturing capabilities—if SMIC fails to co-develop compatible processes, LogicFolding risks remaining a paper tiger. The real test is whether a closed-loop ecosystem (tools, IPs, volume production) materializes by 2027.