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Blogs SUSE, Openchip Partner To Build Europe’s First Digitally Sovereign RISC-V Stack By Jiya Jay Singh - June 30, 2026 0 10 SUSE Logo (PRNewsFoto/SUSE) SUSE and Openchip have signed an MoU to native-certify enterprise software on European-designed RISC-V accelerators, offering an open alternative to overseas chip monopolies. SUSE, an open-source enterprise software group, and Openchip, a Spanis

RISC-V Open Source European Chips Digital Sovereignty Chip Independence Cloud Computing Artificial Intelligence Data Security

Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna) - Semiconductor Engineering

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semiengineering.com 2026-06-30 Semiconductor Engineering

Researchers from ETH Zurich, lowRISC, and University of Bologna published a technical paper titled “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.” This paper describes Croc, an open-source, customizable RISC-V SoC platform and teaching flow that lets students take domain-specific chip-design projects from architecture and RTL through physical

RISC-V Open Source Chip Design Semiconductor Education SoC Platform RTL Design Physical Design Silicon Manufacturing

Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI

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eetimes.com 2026-06-30

RISC-V heavyweights tackle physical AI, edge autonomy and TOPS-per-watt—watch how robots chase their killer app.

Physical AI RISC-V Ecosystem Edge Intelligence Chip Design AI Hardware Embedded Systems Computing Architecture

Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI - EE Times

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news.google.com 2026-06-30 EE Times

AheadComputing Positions RISC-V CPU Strategy Around AI Infrastructure Bottlenecks - TipRanks

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www.tipranks.com 2026-06-29 TipRanks

www.tipranks.com Performing security verification This website uses a security service to protect against malicious bots. This page is displayed while the website verifies you are not a bot. Ray ID: a17736143c7bdc5f Performance and Security by Cloudflare Privacy

RISC-V AI Infrastructure CPU Architecture Semiconductor Chips Artificial Intelligence Computing Chip Design Technology Strategy Computing Architecture

SUSE & Openchip back European RISC-V software stack - ChannelLife UK

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channellife.co.uk 2026-06-29 ChannelLife UK

VIRTUALISATION DATA PROTECTION DC SUSE & Openchip back European RISC-V software stack Mon, 29th Jun 2026 SEAN MITCHELL Publisher SUSE and Openchip have signed a memorandum of understanding to develop a European RISC-V hardware and open source software stack, centred on software support for processors designed in Europe. The work will focus on tuning SUSE Linux and Kubernetes products for Openchi

RISC-V Open Source Software European Semiconductor Data Sovereignty Cloud Computing Containerization Artificial Intelligence Chip Design

WCH CH32V006EVT board supports Zephyr for low-cost RISC-V development - LinuxGizmos.com

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linuxgizmos.com 2026-06-28 LinuxGizmos.com

Olimex recently featured the WCH CH32V006EVT, a low-cost evaluation board for the RISC-V-based CH32V006K8U6 microcontroller. The board is designed around WCH’s CH32V006 family and provides a compact platform for experimenting with the QingKe V2C 32-bit RISC-V core, Zephyr support, and basic embedded development features. The CH32V006K8U6 integrates a QingKe V2C processor using the RV32EmC instruc

RISC-V Microcontroller Zephyr OS Embedded Development WCH CH32V006 Open Source Hardware Low Power Design

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