tomshardware.com
2026-08-20
Synopsys has released silicon validation results for its first 3D-stacked PCIe 6.0 test chip, built on a 5nm process and achieving 64 GT/s per lane with a total bandwidth of up to 128 GB/s across an eight-lane link using PAM4 signaling. The chip was realized by deconstructing a prior 2D PCIe 6.0 des