Semiconductor News & Analysis Feed

PRESS RELEASE — Researchers led by Illinois Grainger Engineering professor Qing Cao have demonstrated a scalable way to directly and sequentially stack high-performance silicon circuits. This advance marks a critical step toward realizing the full potential of three-dimensional chips that could carry computing beyond the limits of traditional scaling. For more than half a century, the power of co

Tech Industry Manufacturing Semiconductors Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture — 3D design delivers increased performance and better thermal management News By Luke James published 20 minutes ago China now has a prototype tool designed for vertical circuit stacking. (Image credit: Getty Images) Share this article 0 Join the conversatio

The announcement came two days after Huawei presented LogicFolding and its accompanying Tau Scaling Law at ISCAS 2026.