Imec, Sony unveil backside interconnect method for 3D chip stacking

The backside interconnect method co-developed by imec and Sony bypasses traditional TSV bottlenecks in 3D stacking—addressing thermal density and routing congestion—to enable tighter logic-memory integration. This will force rapid upgrades across EDA tools, advanced packaging materials, and wafer-level metrology, particularly benefiting heterogeneous integration approaches outside TSMC’s CoWoS or Intel’s Foveros. Compliance risks loom if the process relies on EUV or precision bonding tools subject to U.S.-Netherlands export controls, pushing Japanese and European firms to build non-U.S. equipment redundancy. In response to TSMC’s lead in 3D Fabric, Samsung and Intel are likely to accelerate hybrid bonding and backside power delivery (BSPDN) investments to retain HPC clients. Within 18 months, this could seed next-gen AI chip architectures—but yield stability and thermal management remain critical long-tail hurdles for datacenter adoption.