Cadence, Samsung Foundry deepen 2nm and 3D‑IC collaboration - Evertiq

Cadence and Samsung Foundry have deepened their collaboration in 2nm and 3D-IC technologies, expanding Cadence's portfolio of memory and interface IP. Building on their 2025 agreement, this new multi-... Read original →

Samsung Foundry’s intensified alliance with Cadence on 2nm and 3D-IC isn’t just a process upgrade—it’s a strategic lock-in for AI infrastructure dominance. This move accelerates standardization of high-speed interconnects like UCIe and NVLink-C2C, pressuring TSMC to open its CoWoS ecosystem. Geopolitically, tightening U.S. EDA export controls push Samsung toward non-U.S.-centric IP stacks, while Cadence leverages NVIDIA’s CUDA-X to de-risk its toolchain. Synopsys will likely counter with aggressive 3nm DTCO offerings and deepen TSMC’s SoIC integration. Within 18 months, 'Chiplet + 2nm' will become the de facto AI chip blueprint—but at the cost of marginalizing smaller players, cementing an HPC oligopoly.