Semiconductor News & Analysis Feed

The surge in demand for AI and HPC devices is driving the semiconductor industry toward panel-level packaging (PLP) to accommodate increasingly large chip sizes. HDFO panel packaging requires higher RDL layer counts, increased micropillar height, and reduced trace and bump pitches, posing new challe

At TSMC's recent European Technology Symposium, the company stated that although panel-level packaging technologies can enable significantly larger chip packages, they will not replace current wafer-level packaging solutions like CoWoS in the near term. While panel-based processes offer advantages i

At TSMC's recent European Technology Symposium, senior vice president Kevin Zhang emphasized that while panel-level packaging technologies offer potential for larger chip packages, they will not replace current wafer-level packaging solutions like CoWoS in the near term. Although panel-based process

At TSMC's European Technology Symposium on June 16, 2026, senior vice president Kevin Zhang emphasized the advantages of CoWoS (Chip on Wafer on Substrate) over panel-level packaging technologies like CoPoS for large AI chips. Zhang noted that while panel-level approaches offer scalability in physic