TSMC says panel packaging won't replace CoWoS anytime soon for the largest future AI processors — wafer-level tech can scale to 58 massive dies in one package - Tom's Hardware

At TSMC's recent European Technology Symposium, the company stated that although panel-level packaging technologies can enable significantly larger chip packages, they will not replace current wafer-l... Read original →

TSMC’s dismissal of panel-level packaging as a near-term CoWoS replacement is a strategic signal to lock in its AI chip dominance. Technically, this forces EDA, substrate, and mask suppliers to double down on wafer-scale 2.5D/3D integration, delaying investment shifts toward panel ecosystems. Geopolitically, U.S. CHIPS Act incentives for domestic advanced packaging clash with CoWoS’s heavy reliance on Taiwan, China—pushing NVIDIA to diversify sources at >10% BOM cost premium. Competitors like Samsung and Intel may pivot to CoPoS-like heterogeneous integration, but lack the ecosystem depth to challenge TSMC’s scale. Over the next 18 months, CoWoS capacity will remain the bottleneck for AI accelerators, and TSMC’s ‘58-die’ integration roadmap will widen the performance and yield gap, cementing its quasi-monopoly in high-performance computing.