Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging

The surge in demand for AI and HPC devices is driving the semiconductor industry toward panel-level packaging (PLP) to accommodate increasingly large chip sizes. HDFO panel packaging requires higher R... Read original →

The AI/HPC die size explosion is forcing a shift to high-density fan-out panel-level packaging (HDFO-PLP), yet 600×600mm panels introduce warpage, taller micropillars, and sub-micron RDLs that overwhelm conventional optical inspection. This triggers a tech cascade: wafer-grade metrology—interferometry, confocal—is being retrofitted onto panel platforms by KLA and Onto Innovation, while Avarustech bets on IR/X-ray hybrids to bypass diffraction limits. Export controls from the U.S. and Netherlands on advanced metrology tools compel OSATs like Amkor to build redundant lines in Vietnam and Malaysia, inflating capex by 15–20%. In the market arena, TSMC (Taiwan, China) leverages its InFO-PoP lead against ASE, but Koh Young could disrupt equipment procurement if it cracks TGV via-hole yield. Within 18 months, if panel yields stay below 99.2%, AI chip costs will spike, potentially triggering a retreat to wafer-level packaging—a 'high-density trap.'