Semiconductor News & Analysis Feed

This article delves into the data transmission bottleneck in modern AI computing, shifting focus from computational capability to data delivery efficiency. The analysis compares three leading memory architectures - HBC (High Bandwidth Cache), HBM (High Bandwidth Memory), and SRAM (Static Random Acce

This is the second part of a semiconductor memory technology comparison analysis, presenting an architect's perspective on evaluating HBC (High Bandwidth Cache), HBM (High Bandwidth Memory), and SRAM (Static Random Access Memory) for AI inference applications. Building upon the first part's comparis

As demand for AI inference grows, traditional High Bandwidth Memory (HBM) is facing challenges in power efficiency and data handling. The semiconductor industry is now developing next-generation memory technologies such as High Bandwidth Compute (HBC), High Bandwidth Flash (HBF), and Z-Angle Memory

Qualcomm unveiled its latest AI data center platform Dragonfly at its annual investor day, introducing a new technology called High Bandwidth Compute (HBC) as a key strategy to compete against NVIDIA, AMD, and AI chip startups. This move demonstrates Qualcomm's strategic expansion from mobile commun

Qualcomm unveiled its High-Bandwidth Compute (HBC) near-memory computing architecture aimed at overcoming the 'memory wall' that limits many AI workloads. By decoupling the AI accelerator from the SoC and placing it beneath the LPDDR DRAM stack, Qualcomm achieves high bandwidth and capacity without

Qualcomm has unveiled its High-Bandwidth Compute (HBC) near-memory AI architecture, designed to break the memory wall that limits performance in many AI workloads. By decoupling the AI accelerator from the SoC and placing it beneath the LPDDR DRAM stack, Qualcomm claims HBC delivers 6x higher bandwi

Qualcomm unveiled its breakthrough technology HBC (High-Bandwidth Compute) at its 2026 Investors Day, targeting the AI data center market to overcome the memory wall bottleneck. HBC employs a novel 3D-stacked chip architecture that integrates compute and memory closely, delivering significant improv