Semiconductor News & Analysis Feed

Taiwan Semiconductor Manufacturing Company (TSMC) is accelerating development of a next-generation AI chip packaging technology called CoPoS, shifting production from traditional 12-inch wafers to 310mm x 310mm square panels. According to DigiTimes, mass production is expected to begin in 2029. TSMC

TSMC is advancing its strategic positioning in the AI chip market by targeting commercialization of panel-level CoPoS (Chip on Panel System) packaging by 2029. This packaging technology represents a significant leap in integrating multiple chips on a single panel, enabling more compact designs and h

Taiwan Semiconductor Manufacturing Company (TSMC) is aggressively advancing CoPoS (Chip-on-Panel-on-Substrate) packaging to replace the existing CoWoS (Chip-on-Wafer-on-Substrate) technology in response to rising demand for AI and compute-intensive applications. Central to this shift is the adoption

Taiwan Semiconductor Manufacturing Company (TSMC) is aggressively advancing CoPoS (Chip-on-Panel-on-Substrate) packaging to replace the existing CoWoS (Chip-on-Wafer-on-Substrate) technology, driven by the growing demand for AI and high-performance computing. CoPoS utilizes glass core substrates, wh