TSMC targets 2029 for panel-level CoPoS packaging in AI chip push - DigiTimes - Yahoo Finance

Taiwan Semiconductor Manufacturing Company (TSMC) is accelerating development of a next-generation AI chip packaging technology called CoPoS, shifting production from traditional 12-inch wafers to 310... Read original →

TSMC’s push toward CoPoS panel-level packaging by 2029 is a strategic bet to overcome both physical scaling limits and cost inefficiencies in AI chips. Technically, the shift to 310mm square glass substrates forces material suppliers to develop ultra-low CTE glass and compels equipment makers to reinvent lithography and metrology for large-format redistribution layers—raising entry barriers. From a compliance standpoint, tighter integration with Taiwan, China-based partners increases supply chain concentration risk amid U.S.-EU localization mandates. Intel will likely accelerate Foveros Direct integration with glass substrates, while Samsung may pivot through its H-Cube architecture. Although mass production remains years away, CoPoS has already triggered a de facto standard lock-in: competitors are now constrained to react within TSMC’s defined technological envelope, cementing its dominance in the AI manufacturing stack.