The global semiconductor industry is undergoing a silent yet profound structural split: on one side, a handful of players can still shrink transistors; on the other, aspirants are firmly locked into mature nodes by geopolitical constraints and equipment bans. Across this widening technological chasm, TSMC is leveraging its System-on-Integrated-Chips (SoIC) technology not only to solidify its monopoly in advanced AI chip manufacturing but also to deeply bind leading customers like NVIDIA into its advanced packaging ecosystem. Meanwhile, Huawei—despite remarkable engineering resilience in its Ascend and Kirin chips—has hit a “process wall,” unable to mass-produce below the 7-nanometer node due to restrictions on extreme ultraviolet (EUV) lithography tools.
TSMC’s SoIC is far more than a packaging upgrade; it is a strategic detour around the physical limits of Moore’s Law. As transistor dimensions approach atomic scales, the cost and complexity of traditional scaling rise exponentially. TSMC has pivoted to 3D stacking, die-to-die interconnects, and heterogeneous integration to sustain performance gains at the system level. By 2025, its CoWoS capacity had expanded to 180,000 wafers per month, with over 60% dedicated to NVIDIA’s Blackwell and upcoming B200 AI accelerators. This allocation isn’t merely market-driven—it reflects technical path dependency. NVIDIA’s AI architecture relies heavily on TSMC’s CoWoS and SoIC to tightly couple high-bandwidth memory (HBM) with compute dies. Without this packaging platform, chip performance would degrade significantly. This “lock-in” effect elevates TSMC from a foundry to an invisible architect of AI infrastructure.
Huawei’s predicament, by contrast, is steeped in geopolitics. Although its Mate 60 series, launched in 2023, featured the Kirin 9000S—a chip widely believed to be manufactured by SMIC using a 7nm-equivalent process—the reality is more nuanced. That node was achieved through aggressive multi-patterning with deep ultraviolet (DUV) lithography, resulting in low yields, high costs, and poor scalability. Crucially, 7nm represents the current ceiling of China’s semiconductor equipment capabilities. The U.S. Department of Commerce’s October 2022 export controls explicitly banned the sale of tools capable of producing logic chips at 14nm or below—and completely blocked EUV machines. Even with world-class chip design talent, Huawei cannot translate that into continuously iterated advanced products. While the Ascend 910B rivals NVIDIA’s A100 in specific workloads, it lags in energy efficiency and interconnect bandwidth due to process and packaging limitations.
I judge that over the next three years, advanced chipmaking will bifurcate into two tracks. One, led by TSMC and Samsung (for non-China clients), will serve global firms like NVIDIA, AMD, and Apple, relying on 3D integration technologies like SoIC and X-Cube to sustain compute scaling. The other, anchored in China’s domestic supply chain, will focus on optimizing mature nodes (28nm and above) for AI inference, edge computing, and industrial applications. For Huawei to breach the process wall, design innovation alone won’t suffice—it must await breakthroughs in domestic EUV or alternative lithography, a timeline likely exceeding five years.
Notably, TSMC itself faces geopolitical risks. Its Arizona fab’s 5nm production has been repeatedly delayed, and 4nm yields still trail those of its Taiwan, China facilities. This reveals the deep ecosystem dependencies of advanced nodes—on materials, equipment maintenance, and tacit engineering knowledge—that resist simple replication. Yet as long as its Taiwan, China operations remain stable, global AI leaders have no viable alternatives.
At its core, this technological rift is no longer just about commercial competition—it’s a contest of national tech sovereignty. When compute power becomes the new oil, the ability to manufacture advanced chips turns into strategic capital. Huawei’s path forward tests not only HiSilicon’s design prowess but the entire Chinese semiconductor ecosystem’s resilience. Meanwhile, the deep entanglement between TSMC and NVIDIA underscores a harsh truth of the AI era: the most powerful chip company may not be the designer, but the gatekeeper who controls the wafer and the packaging interface.
The critical question remains: as geopolitical forces forcibly fracture technological pathways, can the global semiconductor industry sustain the efficient, open innovation rhythm of the past three decades? Or are we entering a “post-globalized” chip era—one marked by lower efficiency, higher costs, and fragmented innovation?