Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density

At the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, Huawei unveiled a breakthrough chip design framework aimed at narrowing the technological gap with global leaders ... Read original →

Huawei’s 'Tau Scaling Law' and LogicFolding architecture represent a systemic workaround to EUV sanctions—boosting transistor density by 55% through 3D logic stacking, not lithographic scaling. This forces SMIC to accelerate N+4 and 3D NAND integration and compels EDA vendors to overhaul simulation frameworks for folded logic. The U.S. may tighten export controls on advanced packaging tools, raising domestic AI chip production costs. TSMC and NVIDIA will likely fortify their Chiplet ecosystems, but if Huawei demonstrates FP4-HBM synergy in the Mate 90, it could redefine global AI accelerator design. Over the next 18 months, China will channel capital into homegrown IP cores, advanced packaging, and photoresist supply chains, crystallizing a viable 'post-EUV' semiconductor cluster that erodes Moore’s Law’s hegemony in tech standard-setting.