TSMC’s HBM-Packaging Yield Issues Help Intel, Analysts Say

According to Counterpoint Research co-founder Neil Shah and other analysts, TSMC’s challenges in integrating AI accelerators with high-bandwidth memory (HBM) on a single chip have created an opportuni... Read original →

TSMC’s yield issues in integrating HBM with AI accelerators are creating a strategic opening for Intel. The reliance on silicon interposers in CoWoS has led to elevated costs, yield risks, and capacity constraints, particularly for large die manufacturing where defect rates are high. This has prompted some customers to explore alternatives like Intel’s EMIB, ZAM, and XBM technologies, which have already been validated in Sapphire Rapids and Ponte Vecchio. While NVIDIA and AMD remain loyal to TSMC, Google and MediaTek are testing alternatives, signaling a potential shift in supplier dynamics. As 3D chip-stacking and advanced packaging evolve, TSMC’s ability to maintain its lead will depend on rapid CoWoS improvements. Over the next 12–24 months, packaging innovation will be central to AI chip competition, with Intel poised to gain market share.