Qualcomm's new High Bandwidth Compute looks to tackle costs of High Bandwidth Memory - TechRadar

Qualcomm has unveiled its new High Bandwidth Compute (HBC) memory architecture, designed to reduce the cost and power consumption associated with traditional High Bandwidth Memory (HBM). By stacking L... Read original →

Qualcomm’s HBC architecture disrupts the AI data center memory stack by replacing HBM with 3D-stacked LPDDR, directly challenging SK Hynix and Samsung’s pricing dominance and pressuring TSMC (Taiwan, China) to reallocate CoWoS capacity. While sidestepping EUV dependency, HBC’s reliance on TSV processes introduces new supply chain localization risks under U.S. CHIPS Act scrutiny—if classified as export-controlled, Chinese firms face higher costs. NVIDIA may counter by expanding CXL-based Grace Hopper ecosystems, while Intel could accelerate Gaudi3 via its NMC approach. If Microsoft and Meta validate HBC’s claimed efficiency within 18 months, it could spawn a low-power AI accelerator segment, forcing premature HBM4 iteration and eroding DDR5’s foothold in inference workloads.