Qualcomm reveals HBC near-memory AI architecture, AI250 and AI350 accelerators — touts 6x higher bandwidth-per-watt compared to HBM, 200x capacity compared to on-chip SRAM - Tom's Hardware

Qualcomm has unveiled its High-Bandwidth Compute (HBC) near-memory AI architecture, designed to break the memory wall that limits performance in many AI workloads. By decoupling the AI accelerator fro... Read original →

Qualcomm’s HBC architecture represents a structural break from the memory wall dilemma by embedding AI accelerators beneath LPDDR stacks—bypassing HBM’s costly silicon interposers. This directly undermines SK hynix and Samsung’s premium HBM leverage and weakens TSMC’s CoWoS pricing power. Intel and Broadcom will likely fast-track X-DRAM or ZAM alternatives, while GUC in Taiwan, China risks marginalization if DRAM-on-Logic yield lags. Crucially, HBC’s reliance on mature nodes and standard packaging sidesteps advanced packaging export controls, slashing geopolitical supply chain risk. Over the next 12–24 months, data center adopters like Oracle and Anthropic will prioritize its bandwidth-per-watt metric; if AI250/350 deliver, LPDDR could displace HBM as the AI training memory backbone, redefining compute-memory co-design.