Qualcomm reveals HBC near-memory AI architecture, AI250 and AI350 accelerators

Qualcomm unveiled its High-Bandwidth Compute (HBC) near-memory computing architecture aimed at overcoming the 'memory wall' that limits many AI workloads. By decoupling the AI accelerator from the SoC... Read original →

Qualcomm’s HBC architecture sidesteps reliance on HBM and advanced packaging by stacking AI accelerators under LPDDR, targeting the memory wall with superior bandwidth-per-watt. This disrupts SK hynix and Samsung’s HBM5 roadmap and pressures TSMC to reassess CoWoS allocation. Technically, GUC’s DoL and NEO’s X-DRAM may converge with HBC, spurring new heterogeneous memory interface standards. Geopolitically, tighter U.S. export controls on advanced packaging could inadvertently favor HBC’s supply chain resilience. Competitively, NVIDIA may enhance Grace Hopper’s LPDDR compatibility, while AMD accelerates HBM cost reduction for MI300X. Within 18 months, 'bandwidth efficiency' will emerge as a key data center AI metric; if HBC achieves viable yields, it could structurally displace HBM in edge inference, redefining compute-memory co-design.