[News] TSMC Plans Mini-Loop at Kaohsiung to Speed CoWoS Tool Validation; Reportedly Eyes AUO Site for CoPoS - TrendForce

TSMC's dual-track strategy—accelerating CoWoS validation infrastructure while simultaneously scouting CoPoS panel-level packaging—reveals a company preparing for a structural shift in advanced packagi... Read original →

TSMC's Kaohsiung Mini-Loop is not a validation shortcut—it is supply-chain sovereignty. With CoWoS capacity compounding at 80% CAGR through 2027, no external OSAT can sustain the R&D cadence AI chiplets demand. Internalizing tool qualification demotes ASE and Amkor from partners to execution endpoints, structurally migrating margin upstream. The technical bottleneck is migrating downstream. In the CoWoS era the constraint is silicon-interposer RDL pitch and HBM stack yield; in the CoPoS era it becomes TGV aspect-ratio control, sub-micron ultrafast-laser precision, and panel-level wet-etch uniformity. Materials science is displacing lithography as the primary constraint. Applied Materials and Lam Research have an 18-month window to deliver panel-scale TGV production; miss it and they are out of the core stack. Intel's EMIB-T is already on the panel-level starting line but lacks TSMC's customer lock-in and scale. The real contest is ecosystem position: TSMC is building a closed design-plus-packaging operating system that reduces competitors' packaging to an optional add-on. Critical 12-to-24-month inflection: CoWoS-L yield crossing 95% in H2 2025 shifts the bottleneck from feasibility to volume. If glass-substrate TGV yield clears 90% by Q2 2026, CoPoS enters irreversible production. The 300mm round-wafer ceiling gets permanently bypassed.