MediaTek pins second ASIC project and customer to 2028

MediaTek's dual-customer ASIC roadmap is a structural disruption to the data center custom silicon landscape, not a product update. The second-generation project targeting Q1 2028 confirms first-gen has cleared the full architecture-to-tapeout validation loop. The EMIB packaging choice is strategically loaded: it sidesteps CoWoS capacity constraints and represents a calculated bet on Intel's foundry ecosystem. Running two customers in parallel pushes IP reuse above 60%, but memory controller and PCIe 6.0 PHY customization will scale non-linearly, making Synopsys and Cadence toolchains a hidden bottleneck. Competitively, Broadcom and Marvell have anchored Google and Meta respectively, while NVIDIA pushes NVLink Fusion into semi-custom territory. MediaTek's entry window aligns precisely with the 2026-2028 transition from monolithic to multi-chip-let architectures, where EMIB's 2.5D interconnect density is a natural fit. The critical risk: if the US Commerce Department extends export controls to data center ASIC design tools—mirroring the October 2023 HBM and advanced packaging restrictions—IP transfer between MediaTek's design centers in Taiwan, China and overseas customers will face compliance friction, potentially inflating operational costs by 15-20%. 12-24 month outlook: expect third-gen architecture pre-research by H2 2026. If the second customer's revenue validates platform scalability, the ASIC market shifts from a Broadcom/Marvell duopoly to a three-pole contest, compressing the 45-50% gross margin ceiling and forcing the competitive axis from "who can build" to "whose cost structure wins."